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| r8c/l35c group, r8c/l36c group, r8c/l38c group, r8c/l3ac group renesas mcu datasheet r01ds0095ej0101 rev.1.01 page 1 of 72 apr 15, 2011 1. overview 1.1 features the r8c/l35c group, r8c/l36c group, r8c/l38c group, and r8c/l3ac group of single-chip mcus incorporate the r8c cpu core, which implements a powerful instruction set for a high level of efficiency and supports a 1 mbyte address space, allowing execution of instructions at high speed. in addition, the cpu core integrates a multiplier for high-speed operation processing. power consumption is low, and the supported operating modes allow additional power control. these mcus are designed to maximize emi/ems performance. integration of many peripheral functions, including mult ifunction timer and serial interface, helps reduce the number of system components. these groups have data flash (1 kb 4 blocks) with the background operation (bgo) function. 1.1.1 applications household appliances, office equipment, au dio equipment, consumer products, etc. r01ds0095ej0101 rev.1.01 apr 15, 2011
r8c/l35c group, r8c/l36c group, r8c/l3 8c group, r8c/l3ac group 1. overview r01ds0095ej0101 rev.1.01 page 2 of 72 apr 15, 2011 1.1.2 differences between groups table 1.1 lists the differences between groups, table 1.2 lists the programmable i/o ports provided for each group, and table 1.3 lists the lcd display function pins provided for each group. figures 1.9 to 1.13 show the pin assignment for each group, and tables 1.7 to 1.10 list product information. the explanations in the chapters wh ich follow apply to the r8c/l3ac group only. note the differences shown below. note: 1. i/o ports are shared with i/o functi ons, such as interrupts or timers. refer to tables 1.11 to 1.13, pin name information by pin number , for details. table 1.1 differences between groups item function r8c/l35c group r8c/l36c group r8c/l38c group r8c/l3ac group i/o ports programmable i/o ports 41 pins 52 pins 68 pins 88 pins high current drive ports 5 pins 8 pins 8 pins 16 pins interrupts int interrupt pins 5 pins 8 pins 8 pins 8 pins key input interrupt pins 4 pins 4 pins 8 pins 8 pins timer ra timer ra output pin none 1 pin 1 pin 1 pin timer rb timer rb output pin none 1 pin 1 pin 1 pin timer rd timer rd i/o pin none none 8 pins 8 pins timer re timer re output pin none 1 pin 1 pin 1 pin timer rg timer rg i/o pin none none none 2 pins timer rg output pin none none none 2 pins a/d converter analog input pin 10 pins 10 pins 16 pins 20 pins lcd drive control circuit lcd power supply 3 pins (vl1, vl2, vl4) 4 pins (vl1 to vl4) 4 pins (vl1 to vl4) 4 pins (vl1 to vl4) common output pins max. 4 pins max. 8 pins max. 8 pins max. 8 pins segment output pins max. 24 pins max. 32 pins max. 48 pins max. 56 pins packages 52-pin lqfp 64-pin lqfp 80-pin lqfp 100-pin lqfp/ 100-pin qfp r8c/l35c group, r8c/l36c group, r8c/l3 8c group, r8c/l3ac group 1. overview r01ds0095ej0101 rev.1.01 page 3 of 72 apr 15, 2011 notes: 1. the symbol ? 3 ? indicates a programmable i/o port. 2. the symbol ? ? ? indicates the settings should be made as follows: - set 1 to the corresponding bits in the pdi (i = 1 to 3, 5 to 7, and 10 to 13) register. - set 0 to the corresponding bits in the pi (i = 1 to 3, 5 to 7, and 10 to 13) register. - set 0 to the corresponding bits in the p10drr or p11drr register. notes: 1. the symbol ? ? ? indicates there is no lcd display function. set the corresponding bits in registers lse1 to lse3, lse5 to lse7 to 0 for these pins. 2. seg52 to seg55 can be used as com7 to com4. the r8c/l35c group does not have pins seg52 to seg55, so 1/8 duty cannot be selected. 3. the r8c/l35c group does not have the vl3 pin, so 1/4 bias cannot be selected. when the internal voltage multiplier is used, 1/2 bias cannot also be selected. table 1.2 programmable i/o ports provided for each group programmable i/o port r8c/l35c group total: 41 i/o pins r8c/l36c group total: 52 i/o pins r8c/l38c group total: 68 i/o pins r8c/l3ac group total: 88 i/o pins bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 p1 ???????????????????? 3 3 3 3 3 3 3 3 3 3 3 3 p2 3 3 3 3 ???? 3 3 3 3 ???? 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 p3 ???? 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 p4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 p5 ???????????????????????????? 3 3 3 3 p6 ???????????????? 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 p7 3 3 3 3 ???? 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 p10 ???????????????????????? 3 3 3 3 3 3 3 3 p11 ??? 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 p12 ???? 3 3 3 3 ???? 3 3 3 3 ???? 3 3 3 3 ???? 3 3 3 3 p13 ???? 3 3 3 3 ???? 3 3 3 3 ???? 3 3 3 3 3 3 3 3 3 3 3 3 table 1.3 lcd display function pins provided for each group shared i/o port l35c group common output: max. 4 segment output: max. 24 l36c group common output: max. 8 segment output: max. 32 l38c group common output: max. 8 segment output: max. 48 l3ac group common output: max. 8 segment output: max. 56 p0 seg 7 seg 6 seg 5 seg 4 seg 3 seg 2 seg 1 seg 0 seg 7 seg 6 seg 5 seg 4 seg 3 seg 2 seg 1 seg 0 seg 7 seg 6 seg 5 seg 4 seg 3 seg 2 seg 1 seg 0 seg 7 seg 6 seg 5 seg 4 seg 3 seg 2 seg 1 seg 0 p1 ???????????????????? seg 11 seg 10 seg 9 seg 8 seg 15 seg 14 seg 13 seg 12 seg 11 seg 10 seg 9 seg 8 p2 seg 23 seg 22 seg 21 seg 20 ???? seg 23 seg 22 seg 21 seg 20 ???? seg 23 seg 22 seg 21 seg 20 seg 19 seg 18 seg 17 seg 16 seg 23 seg 22 seg 21 seg 20 seg 19 seg 18 seg 17 seg 16 p3 ???? seg 27 seg 26 seg 25 seg 24 seg 31 seg 30 seg 29 seg 28 seg 27 seg 26 seg 25 seg 24 seg 31 seg 30 seg 29 seg 28 seg 27 seg 26 seg 25 seg 24 seg 31 seg 30 seg 29 seg 28 seg 27 seg 26 seg 25 seg 24 p4 seg 39 seg 38 seg 37 seg 36 seg 35 seg 34 seg 33 seg 32 seg 39 seg 38 seg 37 seg 36 seg 35 seg 34 seg 33 seg 32 seg 39 seg 38 seg 37 seg 36 seg 35 seg 34 seg 33 seg 32 seg 39 seg 38 seg 37 seg 36 seg 35 seg 34 seg 33 seg 32 p5 ???????????????????????????? seg 43 seg 42 seg 41 seg 40 p6 ???????????????? seg 51 seg 50 seg 49 seg 48 seg 47 seg 46 seg 45 seg 44 seg 51 seg 50 seg 49 seg 48 seg 47 seg 46 seg 45 seg 44 p7 com 0 com 1 com 2 com 3 ???? com 0 com 1 com 2 com 3 seg 55 seg 54 seg 53 seg 52 com 0 com 1 com 2 com 3 seg 55 seg 54 seg 53 seg 52 com 0 com 1 com 2 com 3 seg 55 seg 54 seg 53 seg 52 p12 ???? cl2 cl1 ?????? cl2 cl1 ?????? cl2 cl1 ?????? cl2 cl1 ?? ? vl1 vl1 vl1 vl1 ? vl2 vl2 vl2 vl2 ?? vl3 vl3 vl3 ? vl4 vl4 vl4 vl4 r8c/l35c group, r8c/l36c group, r8c/l3 8c group, r8c/l3ac group 1. overview r01ds0095ej0101 rev.1.01 page 4 of 72 apr 15, 2011 1.1.3 specifications tables 1.4 to 1.6 list the specifications. table 1.4 specifications (1) item function specification cpu central processing unit r8c cpu core ? number of fundamental instructions: 89 ? minimum instruction execution time: 50 ns (f(xin) = 20 mhz, vcc = 2.7 to 5.5 v) 200 ns (f(xin) = 5 mhz, vcc = 1.8 to 5.5 v) ? multiplier: 16 bits 16 bits 32 bits ? multiply-accumulate instruction: 16 bits 16 bits + 32 bits 32 bits ? operating mode: single-chip mode (address space: 1 mbyte) memory rom/ram data flash refer to tables 1.7 to 1.10 product lists . power supply voltage detection voltage detection circuit ? power-on reset ? voltage detection 3 (detection level of voltage detection 0 and voltage detection 1 selectable) i/o ports programmable i/o ports r8c/l35c group ? cmos i/o ports: 41 , selectable pu ll-up resistor ? high current drive ports: 5 r8c/l36c group ? cmos i/o ports: 52 , selectable pu ll-up resistor ? high current drive ports: 8 r8c/l38c group ? cmos i/o ports: 68 , selectable pu ll-up resistor ? high current drive ports: 8 r8c/l3ac group ? cmos i/o ports: 88, selectable pull-up resistor ? high current drive ports: 16 clock clock generation circuits 4 circuits: xin clock oscillation circuit xcin clock oscillation circuit (32 khz) high-speed on-chip oscillator (with frequency adjustment function) low-speed on-chip oscillator ? oscillation stop detection: xin clock oscillation stop detection function ? frequency divider circuit: division ratio selectable from 1, 2, 4, 8, and 16 ? low-power-consumption modes: standard operating mode (high-speed clock, low-speed clock, high- speed on-chip oscillator, low-speed on-chip oscillator), wait mode, stop mode, power-off mode real-time clock (timer re) interrupts r8c/l35c group ? number of interrupt vectors: 69 ? external interrupt: 9 (int 5, key input 4) ? priority levels: 7 levels r8c/l36c group ? number of interrupt vectors: 69 ? external interrupt: 12 (int 8, key input 4) ? priority levels: 7 levels r8c/l38c group ? number of interrupt vectors: 69 ? external interrupt: 16 (int 8, key input 8) ? priority levels: 7 levels r8c/l3ac group ? number of interrupt vectors: 69 ? external interrupt: 16 (int 8, key input 8) ? priority levels: 7 levels watchdog timer ? 14 bits 1 (with prescaler) ? selectable reset start function ? selectable low-speed on-chip oscillator for watchdog timer dtc (data transfer controller) ? 1 channel ? activation sources: 38 ? transfer modes: 2 (nor mal mode, repeat mode) r8c/l35c group, r8c/l36c group, r8c/l3 8c group, r8c/l3ac group 1. overview r01ds0095ej0101 rev.1.01 page 5 of 72 apr 15, 2011 note: 1. this applies when four pins are selected for common output. table 1.5 specifications (2) item function specification timer timer ra 8 bits 1 (with 8-bit prescaler) timer mode (period timer), pulse output mode (output level inverted every period), event counter mode, pulse width measurement mode, pulse period measurement mode timer rb 8 bits 1 (with 8-bit prescaler) timer mode (period timer), programmable waveform generation mode (pwm output), programmable one-shot gener ation mode, programmable wait one- shot generation mode timer rc 16 bits 1 (with 4 capture/compare registers) timer mode (input capture function, output compare function), pwm mode (output: 3 pins), pwm2 mode (pwm output: 1 pin) timer rd 16 bits 2 (with 4 capture/compare registers) timer mode (input capture function, output compare function), pwm mode (output: 6 pins), reset synchronous pw m mode (three-phase waveform output: 6 pins, sawtooth wave modulation), complementary pwm mode (three-phase waveform output: 6 pins, triangular wave modulation), pwm3 mode (pwm output with fixed period: 2 pins) timer re 8 bits 1 real-time clock mode (counting of se conds, minutes, hours, days of week), output compare mode timer rg 16 bits 1 phase-counting mode, timer mode (output compare func tion, input capture function), pwm mode (output: 1 pin) serial interface uart0, uart1 clock synchronous serial i/o/uart 2 channels uart2 clock synchronous serial i/o/uart, i 2 c mode (i 2 c-bus), multiprocessor communication function synchronous serial communication unit (ssu) 1 (shared with i 2 c-bus) i 2 c bus 1 (shared with ssu) lin module hardware lin: 1 ch annel (timer ra, uart0 used) a/d converter r8c/l35c group 10-bit resolution 10 channels, including sample and hold function, with sweep mode r8c/l36c group 10-bit resolution 10 channels, including sample and hold function, with sweep mode r8c/l38c group 10-bit resolution 16 channels, including sample and hold function, with sweep mode r8c/l3ac group 10-bit resolution 20 channels, including sample and hold function, with sweep mode d/a converter 8-bit resolution 2 circuits comparator b 2 circuits lcd drive control circuit r8c/l35c group common output: max. 4 pins segment output: max. 24 pins bias: 1/2, 1/3 duty: static, 1/2, 1/3, 1/4 r8c/l36c group common output: max. 8 pins segment output: max. 32 pins (1) bias: 1/2, 1/3, 1/4 duty: static, 1/2, 1/3, 1/4, 1/8 r8c/l38c group common output: max. 8 pins segment output: max. 48 pins (1) r8c/l3ac group common output: max. 8 pins segment output: max. 56 pins (1) voltage multiplier and dedica ted regulator integrated r8c/l35c group, r8c/l36c group, r8c/l3 8c group, r8c/l3ac group 1. overview r01ds0095ej0101 rev.1.01 page 6 of 72 apr 15, 2011 table 1.6 specifications (3) note: 1. specify the d version if d ve rsion functions are to be used. item specification flash memory ? programming and eras ure voltage: vcc = 2.7 to 5.5 v ? programming and erasure enduranc e: 10,000 times (data flash) 1,000 times (program rom) ? program security: rom code protect, id code check ? on-chip debug function ? on-board flash rewrite function ? background operation (bgo) function operating frequency/ supply voltage f(xin) = 20 mhz (vcc = 2.7 to 5.5 v) f(xin) = 5 mhz (vcc = 1.8 to 5.5 v) current consumption typ. 7 ma (vcc = 5.0 v, f(xin) = 20 mhz) typ. 3.6 ma (vcc = 3.0 v, f(xin) = 10 mhz) typ. 3.5 a (vcc = 3.0 v, wait mode (f(xcin) = 32 khz)) typ. 2 a (vcc = 3.0 v, stop mode) typ. 0.02 a (vcc = 3.0 v, power-off mode) operating ambient temperature -20 to 85 c (n version) -40 to 85 c (d version) (1) r8c/l35c group, r8c/l36c group, r8c/l3 8c group, r8c/l3ac group 1. overview r01ds0095ej0101 rev.1.01 page 7 of 72 apr 15, 2011 1.2 product lists tables 1.7 to 1.10 list product list for each group. figures 1.1 to 1.4 show the correspondence of part no., with memory size and package for each group. table 1.7 product list for r8c/l35c group current of apr 2011 figure 1.1 correspondence of part no., with memory size and package of r8c/l35c group part no. internal rom capacity internal ram capacity package type remarks program rom data flash r5f2l357cnfp 48 kbytes 1 kbyte 4 6 kbytes plqp0052ja-a n version r5f2l358cnfp 64 kbytes 1 kbyte 4 8 kbytes plqp0052ja-a r5f2l35acnfp 96 kbytes 1 kbyte 4 10 kbytes plqp0052ja-a r5f2l35ccnfp 128 kbytes 1 kbyte 4 10 kbytes plqp0052ja-a r5f2l357cdfp 48 kbytes 1 kbyte 4 6 kbytes plqp0052ja-a d version r5f2l358cdfp 64 kbytes 1 kbyte 4 8 kbytes plqp0052ja-a r5f2l35acdfp 96 kbytes 1 kbyte 4 10 kbytes plqp0052ja-a r5f2l35ccdfp 128 kbytes 1 kbyte 4 10 kbytes plqp0052ja-a part no. r 5 f 2l 35 c c n fp package type: fp: lqfp (0.65 mm pin pitch) classification n: operating ambient temperature -20c to 85c d: operating ambient temperature -40c to 85c rom capacity 7: 48 kb 8: 64 kb a: 96 kb c: 128 kb r8c/l35c group r8c/lx series memory type f: flash memory renesas mcu renesas semiconductor r8c/l35c group, r8c/l36c group, r8c/l3 8c group, r8c/l3ac group 1. overview r01ds0095ej0101 rev.1.01 page 8 of 72 apr 15, 2011 table 1.8 product list for r8c/l36c group current of apr 2011 figure 1.2 correspondence of part no., with memory size and package of r8c/l36c group part no. internal rom capacity internal ram capacity package type remarks program rom data flash r5f2l367cnfp 48 kbytes 1 kbyte 4 6 kbytes plqp0064kb-a n version R5F2L367CNFA 48 kbytes 1 kbyte 4 6 kbytes plqp0064ga-a r5f2l368cnfp 64 kbytes 1 kbyte 4 8 kbytes plqp0064kb-a r5f2l368cnfa 64 kbytes 1 kbyte 4 8 kbytes plqp0064ga-a r5f2l36acnfp 96 kbytes 1 kbyte 4 10 kbytes plqp0064kb-a r5f2l36acnfa 96 kbytes 1 kbyte 4 10 kbytes plqp0064ga-a r5f2l36ccnfp 128 kbytes 1 kbyte 4 10 kbytes plqp0064kb-a r5f2l36ccnfa 128 kbytes 1 kbyte 4 10 kbytes plqp0064ga-a r5f2l367cdfp 48 kbytes 1 kbyte 4 6 kbytes plqp0064kb-a d version r5f2l367cdfa 48 kbytes 1 kbyte 4 6 kbytes plqp0064ga-a r5f2l368cdfp 64 kbytes 1 kbyte 4 8 kbytes plqp0064kb-a r5f2l368cdfa 64 kbytes 1 kbyte 4 8 kbytes plqp0064ga-a r5f2l36acdfp 96 kbytes 1 kbyte 4 10 kbytes plqp0064kb-a r5f2l36acdfa 96 kbytes 1 kbyte 4 10 kbytes plqp0064ga-a r5f2l36ccdfp 128 kbytes 1 kbyte 4 10 kbytes plqp0064kb-a r5f2l36ccdfa 128 kbytes 1 kbyte 4 10 kbytes plqp0064ga-a part no. r 5 f 2l 36 c c n fp package type: fp: lqfp (0.50 mm pin pitch) fa: lqfp (0.80 mm pin pitch) classification n: operating ambient temperature -20c to 85c d: operating ambient temperature -40c to 85c rom capacity 7: 48 kb 8: 64 kb a: 96 kb c: 128 kb r8c/l36c group r8c/lx series memory type f: flash memory renesas mcu renesas semiconductor r8c/l35c group, r8c/l36c group, r8c/l3 8c group, r8c/l3ac group 1. overview r01ds0095ej0101 rev.1.01 page 9 of 72 apr 15, 2011 table 1.9 product list for r8c/l38c group current of apr 2011 figure 1.3 correspondence of part no., with memory size and package of r8c/l38c group part no. internal rom capacity internal ram capacity package type remarks program rom data flash r5f2l387cnfp 48 kbytes 1 kbyte 4 6 kbytes plqp0080kb-a n version r5f2l387cnfa 48 kbytes 1 kbyte 4 6 kbytes plqp0080ja-a r5f2l388cnfp 64 kbytes 1 kbyte 4 8 kbytes plqp0080kb-a r5f2l388cnfa 64 kbytes 1 kbyte 4 8 kbytes plqp0080ja-a r5f2l38acnfp 96 kbytes 1 kbyte 4 10 kbytes plqp0080kb-a r5f2l38acnfa 96 kbytes 1 kbyte 4 10 kbytes plqp0080ja-a r5f2l38ccnfp 128 kbytes 1 kbyte 4 10 kbytes plqp0080kb-a r5f2l38ccnfa 128 kbytes 1 kbyte 4 10 kbytes plqp0080ja-a r5f2l387cdfp 48 kbytes 1 kbyte 4 6 kbytes plqp0080kb-a d version r5f2l387cdfa 48 kbytes 1 kbyte 4 6 kbytes plqp0080ja-a r5f2l388cdfp 64 kbytes 1 kbyte 4 8 kbytes plqp0080kb-a r5f2l388cdfa 64 kbytes 1 kbyte 4 8 kbytes plqp0080ja-a r5f2l38acdfp 96 kbytes 1 kbyte 4 10 kbytes plqp0080kb-a r5f2l38acdfa 96 kbytes 1 kbyte 4 10 kbytes plqp0080ja-a r5f2l38ccdfp 128 kbytes 1 kbyte 4 10 kbytes plqp0080kb-a r5f2l38ccdfa 128 kbytes 1 kbyte 4 10 kbytes plqp0080ja-a part no. r 5 f 2l 38 c c n fp package type: fp: lqfp (0.50 mm pin pitch) fa: lqfp (0.65 mm pin pitch) classification n: operating ambient temperature -20c to 85c d: operating ambient temperature -40c to 85c rom capacity 7: 48 kb 8: 64 kb a: 96 kb c: 128 kb r8c/l38c group r8c/lx series memory type f: flash memory renesas mcu renesas semiconductor r8c/l35c group, r8c/l36c group, r8c/l3 8c group, r8c/l3ac group 1. overview r01ds0095ej0101 rev.1.01 page 10 of 72 apr 15, 2011 table 1.10 product list for r8c/l3ac group current of apr 2011 figure 1.4 correspondence of part no., with memory size and package of r8c/l3ac group part no. internal rom capacity internal ram capacity package type remarks program rom data flash r5f2l3a7cnfp 48 kbytes 1 kbyte 4 6 kbytes plqp0100kb-a n version r5f2l3a7cnfa 48 kbytes 1 kbyte 4 6 kbytes prqp0100jd-b r5f2l3a8cnfp 64 kbytes 1 kbyte 4 8 kbytes plqp0100kb-a r5f2l3a8cnfa 64 kbytes 1 kbyte 4 8 kbytes prqp0100jd-b r5f2l3aacnfp 96 kbytes 1 kbyte 4 10 kbytes plqp0100kb-a r5f2l3aacnfa 96 kbytes 1 kbyte 4 10 kbytes prqp0100jd-b r5f2l3accnfp 128 kbytes 1 kbyte 4 10 kbytes plqp0100kb-a r5f2l3accnfa 128 kbytes 1 kbyte 4 10 kbytes prqp0100jd-b r5f2l3a7cdfp 48 kbytes 1 kbyte 4 6 kbytes plqp0100kb-a d version r5f2l3a7cdfa 48 kbytes 1 kbyte 4 6 kbytes prqp0100jd-b r5f2l3a8cdfp 64 kbytes 1 kbyte 4 8 kbytes plqp0100kb-a r5f2l3a8cdfa 64 kbytes 1 kbyte 4 8 kbytes prqp0100jd-b r5f2l3aacdfp 96 kbytes 1 kbyte 4 10 kbytes plqp0100kb-a r5f2l3aacdfa 96 kbytes 1 kbyte 4 10 kbytes prqp0100jd-b r5f2l3accdfp 128 kbytes 1 kbyte 4 10 kbytes plqp0100kb-a r5f2l3accdfa 128 kbytes 1 kbyte 4 10 kbytes prqp0100jd-b part no. r 5 f 2l 3a c c n fp package type: fp: lqfp (0.50 mm pin pitch) fa: qfp (0.65 mm pin pitch) classification n: operating ambient temperature -20c to 85c d: operating ambient temperature -40c to 85c rom capacity 7: 48 kb 8: 64 kb a: 96 kb c: 128 kb r8c/l3ac group r8c/lx series memory type f: flash memory renesas mcu renesas semiconductor r8c/l35c group, r8c/l36c group, r8c/l3 8c group, r8c/l3ac group 1. overview r01ds0095ej0101 rev.1.01 page 11 of 72 apr 15, 2011 1.3 block diagrams figure 1.5 shows a block diagram of r8c/l35c group. figure 1.6 shows a block diagram of r8c/l36c group. figure 1.7 shows a block diagram of r8c/l38c group. figure 1.8 shows a block diagram of r8c/l3ac group. figure 1.5 block diagram of r8c/l35c group watchdog timer (14 bits) system clock generation circuit xin-xout high-speed on-chip oscillator low-speed on-chip oscillator xcin-xcout ram (2) multiplier timers timer ra (8 bits 1) timer rb (8 bits 1) timer rc (16 bits 1) timer rd (16 bits 2) timer re (8 bits 1) timer rg (16 bits 1) r8c cpu core memory r0h r0l r1h r2 r3 r1l a0 a1 fb sb usp isp intb pc flg i/o ports notes: 1. rom capacity varies with mcu type. 2. ram capacity varies with mcu type. a/d converter (10 bits 10 channels) uart or clock synchronous serial i/o (8 bits 3) i 2 c bus or ssu (8 bits 1) lin module 8 port p0 4 port p3 port p4 4 port p2 rom (1) peripheral functions lcd drive control circuit common output: max. 4 pins segment output: max. 24 pins d/a converter (8 bits 2 channels) 5 port p11 4 port p12 4 port p13 4 port p7 8 comparator b dtc voltage detection circuit low-speed on-chip oscillator for watchdog timer r8c/l35c group, r8c/l36c group, r8c/l3 8c group, r8c/l3ac group 1. overview r01ds0095ej0101 rev.1.01 page 12 of 72 apr 15, 2011 figure 1.6 block diagram of r8c/l36c group watchdog timer (14 bits) system clock generation circuit xin-xout high-speed on-chip oscillator low-speed on-chip oscillator xcin-xcout ram (2) multiplier timers timer ra (8 bits 1) timer rb (8 bits 1) timer rc (16 bits 1) timer rd (16 bits 2) timer re (8 bits 1) timer rg (16 bits 1) r8c cpu core memory r0h r0l r1h r2 r3 r1l a0 a1 fb sb usp isp intb pc flg i/o ports notes: 1. rom capacity varies with mcu type. 2. ram capacity varies with mcu type. a/d converter (10 bits 10 channels) uart or clock synchronous serial i/o (8 bits 3) i 2 c bus or ssu (8 bits 1) lin module 8 port p0 8 port p3 port p4 4 port p2 rom (1) peripheral functions lcd drive control circuit common output: max. 8 pins segment output: max. 32 pins d/a converter (8 bits 2 channels) 8 port p11 4 port p12 4 port p13 8 port p7 8 comparator b dtc voltage detection circuit low-speed on-chip oscillator for watchdog timer r8c/l35c group, r8c/l36c group, r8c/l3 8c group, r8c/l3ac group 1. overview r01ds0095ej0101 rev.1.01 page 13 of 72 apr 15, 2011 figure 1.7 block diagram of r8c/l38c group watchdog timer (14 bits) system clock generation circuit xin-xout high-speed on-chip oscillator low-speed on-chip oscillator xcin-xcout ram (2) multiplier timers timer ra (8 bits 1) timer rb (8 bits 1) timer rc (16 bits 1) timer rd (16 bits 2) timer re (8 bits 1) timer rg (16 bits 1) r8c cpu core memory r0h r0l r1h r2 r3 r1l a0 a1 fb sb usp isp intb pc flg i/o ports notes: 1. rom capacity varies with mcu type. 2. ram capacity varies with mcu type. a/d converter (10 bits 16 channels) uart or clock synchronous serial i/o (8 bits 3) i 2 c bus or ssu (8 bits 1) lin module 8 port p0 8 port p3 port p4 8 port p2 rom (1) peripheral functions lcd drive control circuit common output: max. 8 pins segment output: max. 48 pins d/a converter (8 bits 2 channels) 8 port p11 4 port p12 4 port p13 8 port p7 8 comparator b dtc 4 port p1 8 port p6 voltage detection circuit low-speed on-chip oscillator for watchdog timer r8c/l35c group, r8c/l36c group, r8c/l3 8c group, r8c/l3ac group 1. overview r01ds0095ej0101 rev.1.01 page 14 of 72 apr 15, 2011 figure 1.8 block diagram of r8c/l3ac group watchdog timer (14 bits) system clock generation circuit xin-xout high-speed on-chip oscillator low-speed on-chip oscillator xcin-xcout ram (2) multiplier timers timer ra (8 bits 1) timer rb (8 bits 1) timer rc (16 bits 1) timer rd (16 bits 2) timer re (8 bits 1) timer rg (16 bits 1) r8c cpu core memory r0h r0l r1h r2 r3 r1l a0 a1 fb sb usp isp intb pc flg i/o ports notes: 1. rom capacity varies with mcu type. 2. ram capacity varies with mcu type. a/d converter (10 bits 20 channels) uart or clock synchronous serial i/o (8 bits 3) i 2 c bus or ssu (8 bits 1) lin module 8 port p0 8 port p1 8 port p3 4 port p5 port p4 8 port p2 rom (1) peripheral functions lcd drive control circuit common output: max. 8 pins segment output: max. 56 pins d/a converter (8 bits 2 channels) 8 port p6 8 port p10 8 port p11 4 port p12 8 port p13 8 port p7 8 comparator b dtc voltage detection circuit low-speed on-chip oscillator for watchdog timer r8c/l35c group, r8c/l36c group, r8c/l3 8c group, r8c/l3ac group 1. overview r01ds0095ej0101 rev.1.01 page 15 of 72 apr 15, 2011 1.4 pin assignments figures 1.9 to 1.13 show pin assignments (top view). tables 1.11 to 1.13 list the pin name information by pin number. figure 1.9 pin assignment (top view) of plqp0052ja-a package 27 28 29 30 31 32 33 34 35 36 37 38 39 13 12 11 10 9 8 7 6 5 4 3 2 1 p11_3/scs/(cts2/rts2/int3)/ivcmp3 p11_2/sda/sso/(rxd2/scl2/txd2/sda2/int2)/ivref3 p11_1/ssi/(rxd2/scl2/txd2/sda2/int1)/ivcmp1 p11_0/scl/ssck/(clk2/int0)/ivref1 p7_7/com0 p7_6/com1 p7_5/com2 p7_4/com3 p4_7/seg39/trciod/trciob p4_6/seg38/trcioc/trciob p4_5/seg37/trciob p4_4/seg36/trcioa/trctrg p4_3/seg35/trcclk/trctrg p13_2/an2/rxd0 p13_3/an3/clk0 vl4 cl1/p12_2 cl2/p12_3 vl2 vl1 p0_0/seg0/an4 p0_1/seg1/an5 p0_2/seg2/an6 p0_3/seg3/an7 p0_4/seg4/an8 p0_5/seg5/an9 14 15 16 17 18 19 20 21 22 23 24 25 26 52 51 50 49 48 47 46 45 44 43 42 41 40 r8c/l35c group p11_4/traio/(int4/rxd0) p12_0/xin vcc/avcc xcout reset p12_1/xout xcin p13_0/an0/da0 p13_1/an1/da1/txd0 vref wkup0 mode vss/avss p2_7/seg23/ki7 p3_0/seg24/int0 p4_0/seg32/txd1 p4_1/seg33/rxd1 p4_2/seg34/clk1 p3_1/seg25/int1 p3_2/seg26/int2 p3_3/seg27/int3 p0_6/seg6 p0_7/seg7 p2_4/seg20/ki4 p2_5/seg21/ki5 p2_6/seg22/ki6 notes: 1. the pin in parentheses can be assigned by a program. 2. confirm the pin 1 position on the package by referring to the package dimensions. plqp0052ja-a (52p6a-a) (top view) r8c/l35c group, r8c/l36c group, r8c/l3 8c group, r8c/l3ac group 1. overview r01ds0095ej0101 rev.1.01 page 16 of 72 apr 15, 2011 figure 1.10 pin assignment (top view) of plqp0064kb-a and plqp0064ga-a packages 20 21 22 23 24 25 26 27 28 29 30 31 32 19 18 17 61 60 59 58 57 56 55 54 53 52 51 50 49 62 63 64 p7_6/com1 p7_5/com2 p7_4/com3 p7_3/seg55/com4 p7_2/seg54/com5 p7_1/seg53/com6 p7_0/seg52/com7 p4_7/seg39/trciod/trciob p4_6/seg38/trcioc/trciob p4_5/seg37/trciob p4_4/seg36/trcioa/trctrg p4_3/seg35/trcclk/trctrg p4_2/seg34/clk1 p7_7/com0 p11_0/scl/ssck/(clk2/int0)/ivref1 p11_1/ssi/(rxd2/scl2/txd2/sda2/int1)/ivcmp1 p13_3/an3/clk0 vl4 cl1/p12_2 cl2/p12_3 vl3 vl2 vl1 p0_0/seg0/an4 p0_1/seg1/an5 p0_2/seg2/an6 p0_3/seg3/an7 p0_4/seg4/an8 p0_5/seg5/an9 p13_2/an2/rxd0 p13_1/an1/da1/txd0 p13_0/an0/da0 36 37 38 39 40 41 42 43 44 45 46 47 48 33 34 35 13 12 11 10 9 8 7 6 5 4 3 2 116 15 14 p2_7/seg23/ki7 p3_0/seg24/int0 p3_4/seg28/int4 p3_5/seg29/int5 p3_6/seg30/int6 p3_1/seg25/int1 p3_2/seg26/int2 p3_3/seg27/int3 p0_6/seg6 p2_5/seg21/ki5 p2_6/seg22/ki6 p3_7/seg31/int7/adtrg/trctrg p4_0/seg32/txd1 p4_1/seg33/rxd1 p0_7/seg7 p2_4/seg20/ki4 reset p12_1/xout p11_7/treo/(int7/adtrg) p11_6/trbo/(int6) p11_5/trao/(int5) vss/avss p12_0/xin vcc/avcc wkup0 xcin xcout p11_4/traio/(int4/rxd0) p11_3/scs/(cts2/rts2/int3)/ivcmp3 p11_2/sda/sso/(rxd2/scl2/txd2/sda2/int2)/ivref3 vref mode plqp0064kb-a (64p6q-a) plqp0064ga-a (64p6u-a) (top view) r8c/l36c group notes: 1. the pin in parentheses can be assigned by a program. 2. confirm the pin 1 position on the package by referring to the package dimensions. r8c/l35c group, r8c/l36c group, r8c/l3 8c group, r8c/l3ac group 1. overview r01ds0095ej0101 rev.1.01 page 17 of 72 apr 15, 2011 figure 1.11 pin assignment (top view) of plqp0080kb-a and plqp0080ja-a packages 13 12 11 10 9 8 7 6 5 4 3 2 116 15 14 mode xcin vss/avss p12_0/xin vcc/avcc xcout reset p12_1/xout p13_2/an2/rxd0 wkup0 vref p11_7/treo/(int7/adtrg) p11_6/trbo/(int6) p11_5/trao/(int5) p13_1/an1/da1/txd0 p13_0/an0/da0 17 20 19 18 p11_4/traio/(int4/rxd0) p11_3/scs/(cts2/rts2/int3)/ivcmp3 p11_2/sda/sso/(rxd2/scl2/txd2/sda2/int2)/ivref3 p11_1/ssi/(rxd2/scl2/txd2/sda2/int1)/ivcmp1 28 29 30 31 32 33 34 35 36 37 38 39 40 27 26 25 p7_1/seg53/com6 p7_0/seg52/com7 p6_6/seg50/trdioc1 p6_5/seg49/trdiob1 p6_4/seg48/trdioa1 p6_3/seg47/trdiod0 p6_2/seg46/trdioc0 p6_1/seg45/trdiob0 p6_0/seg44/trdioa0/trdclk p4_7/seg39/trciod/trciob p4_6/seg38/trcioc/trciob p4_5/seg37/trciob p7_2/seg54/com5 p7_3/seg55/com4 p7_4/com3 24 23 22 21 p7_5/com2 p7_6/com1 p7_7/com0 p11_0/scl/ssck/(clk2/int0)/ivref1 p2_6/seg22/ki6 p2_7/seg23/ki7 p3_3/seg27/int3 p3_4/seg28/int4 p3_5/seg29/int5 p3_0/seg24/int0 p3_1/seg25/int1 p3_2/seg26/int2 p2_1/seg17/ki1 p2_4/seg20/ki4 p2_5/seg21/ki5 p3_6/seg30/int6 p3_7/seg31/int7/adtrg/trctrg p4_0/seg32/txd1 p2_2/seg18/ki2 p2_3/seg19/ki3 48 49 50 51 52 53 54 55 56 57 58 59 60 45 46 47 44 41 42 43 p4_1/seg33/rxd1 p4_2/seg34/clk1 p4_3/seg35/trcclk/trctrg p4_4/seg36/trcioa/trctrg 73 72 71 70 69 68 67 66 65 64 63 62 61 74 75 76 p0_0/seg0/an4 p0_1/seg1/an5 p0_2/seg2/an6 p0_3/seg3/an7 p0_4/seg4/an8 p0_5/seg5/an9 p0_6/seg6/an10 p0_7/seg7/an11 p1_0/seg8/an12 p1_1/seg9/an13 p1_2/seg10/an14 p1_3/seg11/an15 p2_0/seg16/ki0 vl1 vl2 vl3 77 cl2/p12_3 78 cl1/p12_2 79 vl4 80 p13_3/an3/clk0 r8c/l38c group plqp0080kb-a (80p6q-a) plqp0080ja-a (fp-80wv) (top view) p6_7/seg51/trdiod1 notes: 1. the pin in parentheses can be assigned by a program. 2. confirm the pin 1 position on the package by referring to the package dimensions. r8c/l35c group, r8c/l36c group, r8c/l3 8c group, r8c/l3ac group 1. overview r01ds0095ej0101 rev.1.01 page 18 of 72 apr 15, 2011 figure 1.12 pin assignment (top view) of plqp0100kb-a package 1 2 3 4 5 6 7 8 9 10111213141516171819202122232425 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 1 00 p0_4/seg4/an8 p0_5/seg5/an9 p0_6/seg6/an10 p0_7/seg7/an11 p1_0/seg8/an12 p1_1/seg9/an13 p1_2/seg10/an14 p1_3/seg11/an15 p1_4/seg12 p1_5/seg13 p1_6/seg14 p1_7/seg15 p2_0/seg16/ki0 vl4 cl2/p12_3 p2_4/seg20/ki4 p2_5/seg21/ki5 p2_6/seg22/ki6 p2_7/seg23/ki7 p3_0/seg24/int0 p3_1/seg25/int1 p3_2/seg26/int2 p3_3/seg27/int3 p3_5/seg29/int5 p3_7/seg31/int7/adtrg/trctrg p4_0/seg32/txd1 p4_1/seg33/rxd1 p4_2/seg34/clk1 p4_3/seg35/trcclk/trctrg p4_4/seg36/trcioa/trctrg p4_5/seg37/trciob p4_6/seg38/trcioc/trciob p4_7/seg39/trciod/trciob p3_6/seg30/int6 p3_4/seg28/int4 p13_7/an19/trgclkb cl1/p12_2 vl3 vl2 vl1 p13_4/an16/trgioa p13_5/an17/trgclka p13_6/an18/trgiob p10_4/(trdioa1/ki4) p10_3/(trdiod0/ki3) p10_2/(trdioc0/ki2) p2_1/seg17/ki1 p2_2/seg18/ki2 p2_3/seg19/ki3 p0_3/seg3/an7 p0_2/seg2/an6 p0_1/seg1/an5 p0_0/seg0/an4 vcc/avcc p12_0/xin p12_1/xout vss/avss mode xcin xcout vref p10_6/(trdioc1/ki6) p11_0/scl/ssck/(clk2/int0) /ivref1 p11_1/ssi/(rxd2/scl2/txd2/sda2/int1)/ivcmp1 p13_2/an2/rxd0 p13_3/an3/clk0 p13_0/an0/da0 p13_1/an1/da1/txd0 p11_2/sda/sso/(rxd2/scl2/txd2/sda2/int2)/ivref3 p11_4/traio/(int4/rxd0) p11_5/trao/(int5) wkup0 p11_3/scs/(cts2/rts2/int3)/ivcmp3 p10_5/(trdiob1/ki5) p10_7/(trdiod1/ki7) p10_0/(trdioa0/trdclk/ki0) p10_1/(trdiob0/ki1) r8c/l3ac group reset p11_7/treo/(int7/adtrg) p11_6/trbo/(int6) p5_0/seg40 p5_1/seg41 p7_0/seg52/com7 p6_7/seg51/trdiod1 p6_6/seg50/trdioc1 p6_5/seg49/trdiob1 p6_4/seg48/trdioa1 p7_1/seg53/com6 p5_3/seg43 p6_0/seg44/trdioa0/trdclk p6_1/seg45/trdiob0 p7_5/com2 p7_7/com0 p7_3/seg55/com4 p7_4/com3 p7_2/seg54/com5 p7_6/com1 p5_2/seg42 p6_2/seg46/trdioc0 p6_3/seg47/trdiod0 plqp0100kb-a (100p6q-a) (top view) notes: 1. the pin in parentheses can be assigned by a program. 2. confirm the pin 1 position on the package by referring to the package dimensions. r8c/l35c group, r8c/l36c group, r8c/l3 8c group, r8c/l3ac group 1. overview r01ds0095ej0101 rev.1.01 page 19 of 72 apr 15, 2011 figure 1.13 pin assignment (top view) of prqp0100jd-b package 1 345678910111213 2 100 99 98 97 96 95 94 93 92 91 90 89 88 68 80 79 78 77 76 75 74 73 72 71 70 69 43 31 32 33 34 35 36 37 38 39 40 41 42 44 45 46 47 48 49 50 56 67 66 65 64 63 62 61 60 59 58 57 55 54 53 52 51 87 86 85 84 83 82 81 15 16 17 18 19 20 21 22 23 24 25 14 26 27 28 29 30 r8c/l3ac group prqp0100jd-b (100p6f-a) (top view) vcc/avcc p12_0/xin p12_1/xout vss/avss mode xcin xcout vref p10_6/(trdioc1/ki6) p11_0/scl/ssck/(clk2/int0) /ivref1 p13_2/an2/rxd0 p13_3/an3/clk0 p13_0/an0/da0 p13_1/an1/da1/txd0 p11_2/sda/sso/(rxd2/scl2/txd2/sda2/int2)/ivref3 p11_4/traio/(int4/rxd0) p11_5/trao/(int5) wkup0 p11_3/scs/(cts2/rts2/int3)/ivcmp3 p10_5/(trdiob1/ki5) p10_7/(trdiod1/ki7) reset p11_7/treo/(int7/adtrg) p11_6/trbo/(int6) p10_4/(trdioa1/ki4) p10_3/(trdiod0/ki3) p10_2/(trdioc0/ki2) p1_7/seg15 p2_0/seg16/ki0 p2_4/seg20/ki4 p2_5/seg21/ki5 p2_6/seg22/ki6 p2_7/seg23/ki7 p3_0/seg24/int0 p3_1/seg25/int1 p3_2/seg26/int2 p3_3/seg27/int3 p3_5/seg29/int5 p3_7/seg31/int7/adtrg/trctrg p4_0/seg32/txd1 p4_1/seg33/rxd1 p4_2/seg34/clk1 p4_3/seg35/trcclk/trctrg p4_4/seg36/trcioa/trctrg p4_5/seg37/trciob p4_6/seg38/trcioc/trciob p4_7/seg39/trciod/trciob p3_6/seg30/int6 p3_4/seg28/int4 p2_1/seg17/ki1 p2_2/seg18/ki2 p2_3/seg19/ki3 p1_4/seg12 p1_5/seg13 p1_6/seg14 p0_4/seg4/an8 p0_5/seg5/an9 p0_6/seg6/an10 p0_7/seg7/an11 p1_0/seg8/an12 p1_1/seg9/an13 vl4 cl2/p12_3 p13_7/an19/trgclkb cl1/p12_2 vl3 vl2 vl1 p13_6/an18/trgiob p0_3/seg3/an7 p0_2/seg2/an6 p0_1/seg1/an5 p0_0/seg0/an4 p7_0/seg52/com7 p6_7/seg51/trdiod1 p6_6/seg50/trdioc1 p6_5/seg49/trdiob1 p6_4/seg48/trdioa1 p7_1/seg53/com6 p5_3/seg43 p6_0/seg44/trdioa0/trdclk p6_1/seg45/trdiob0 p7_5/com2 p7_7/com0 p7_3/seg55/com4 p7_4/com3 p7_2/seg54/com5 p7_6/com1 p5_2/seg42 p6_2/seg46/trdioc0 p6_3/seg47/trdiod0 notes: 1. the pin in parentheses can be assigned by a program. 2. confirm the pin 1 position on the package by referring to the package dimensions. p10_1/(trdiob0/ki1) p10_0/(trdioa0/trdclk/ki0) p5_0/seg40 p5_1/seg41 p1_2/seg10/an14 p1_3/seg11/an15 p13_4/an16/trgioa p13_5/an17/trgclka p11_1/ssi/(rxd2/scl2/txd2/sda2/int1)/ivcmp1 r8c/l35c group, r8c/l36c group, r8c/l3 8c group, r8c/l3ac group 1. overview r01ds0095ej0101 rev.1.01 page 20 of 72 apr 15, 2011 notes: 1. the pin in parentheses can be assigned by a program. 2. the number in brackets indicates the pin number for the 100p6f package. table 1.11 pin name information by pin number (1) pin number control pin port i/o pin functions for peripheral modules l3ac (note 2) l38c l36c l35c interrupt timer serial interface ssu i 2 c bus a/d converter, d/a converter, comparator b lcd drive control circuit 1 [3] 806151 p13_3 clk0 an3 2 [4] 1 62 52 p13_2 rxd0 an2 3 [5] 2 63 1 p13_1 txd0 an1/da1 4 [6] 3 64 2 p13_0 an0/da0 5 [7] 413 wkup0 6 [8] 524vref 7 [9] 635mode 8 [10]746 xcin 9 [11] 8 5 7 xcout 10 [12] 9 6 8 reset 11 [13] 10 7 9 xout p12_1 12 [14] 11 8 10 vss/ avss 13 [15] 12 9 11 xin p12_0 14 [16] 13 10 12 vcc/ avcc 15 [17] 14 11 p11_7 (int7 ) treo (adtrg ) 16 [18] 15 12 p11_6 (int6 ) trbo 17 [19] 16 13 p11_5 (int5 ) trao 18 [20] 17 14 13 p11_4 (int4 ) traio (rxd0) 19 [21] 18 15 14 p11_3 (int3 )(cts2 /rts2 )scs ivcmp3 20 [22] 19 16 15 p11_2 (int2 ) (rxd2/scl2/ txd2/sda2) sso sda ivref3 21 [23] 20 17 16 p11_1 (int1 ) (rxd2/scl2/ txd2/sda2) ssi ivcmp1 22 [24] 21 18 17 p11_0 (int0 ) (clk2) ssck scl ivref1 23 [25] p10_7 (ki7 ) (trdiod1) 24 [26] p10_6 (ki6 ) (trdioc1) 25 [27] p10_5 (ki5 ) (trdiob1) 26 [28] p10_4 (ki 4 ) (trdioa1) 27 [29] p10_3 (ki 3 ) (trdiod0) 28 [30] p10_2 (ki 2 ) (trdioc0) 29 [31] p10_1 (ki 1 ) (trdiob0) 30 [32] p10_0 (ki 0 ) (trdioa0/ trdclk) 31 [33] 22 19 18 p7_7 com0 32 [34] 23 20 19 p7_6 com1 33 [35] 24 21 20 p7_5 com2 34 [36] 25 22 21 p7_4 com3 35 [37] 26 23 p7_3 seg55/ com4 36 [38] 27 24 p7_2 seg54/ com5 37 [39] 28 25 p7_1 seg53/ com6 38 [40] 29 26 p7_0 seg52/ com7 39 [41] 30 p6_7 trdiod1 seg51 r8c/l35c group, r8c/l36c group, r8c/l3 8c group, r8c/l3ac group 1. overview r01ds0095ej0101 rev.1.01 page 21 of 72 apr 15, 2011 notes: 1. the pin in parentheses can be assigned by a program. 2. the number in brackets indicates the pin number for the 100p6f package. 3. pins an10 and an11 are not available in the r8c/l35c, and r8c/l36c groups. table 1.12 pin name information by pin number (2) pin number control pin port i/o pin functions for peripheral modules l3ac (note 2) l38c l36c l35c interrupt timer serial interface ssu i 2 c bus a/d converter, d/a converter, comparator b lcd drive control circuit 40 [42] 31 p6_6 trdioc1 seg50 41 [43] 32 p6_5 trdiob1 seg49 42 [44] 33 p6_4 trdioa1 seg48 43 [45] 34 p6_3 trdiod0 seg47 44 [46] 35 p6_2 trdioc0 seg46 45 [47] 36 p6_1 trdiob0 seg45 46 [48] 37 p6_0 trdioa0/ trdclk seg44 47 [49] p5_3 seg43 48 [50] p5_2 seg42 49 [51] p5_1 seg41 50 [52] p5_0 seg40 51 [53] 38 27 22 p4_7 trciod/ trciob seg39 52 [54] 39 28 23 p4_6 trcioc/ trciob seg38 53 [55] 40 29 24 p4_5 trciob seg37 54 [56] 41 30 25 p4_4 trcioa/ trctrg seg36 55 [57] 42 31 26 p4_3 trcclk/ trctrg seg35 56 [58] 43 32 27 p4_2 clk1 seg34 57 [59] 44 33 28 p4_1 rxd1 seg33 58 [60] 45 34 29 p4_0 txd1 seg32 59 [61] 46 35 p3_7 int7 trctrg adtrg seg31 60 [62] 47 36 p3_6 int6 seg30 61 [63] 48 37 p3_5 int5 seg29 62 [64] 49 38 p3_4 int4 seg28 63 [65] 50 39 30 p3_3 int3 seg27 64 [66] 51 40 31 p3_2 int2 seg26 65 [67] 52 41 32 p3_1 int1 seg25 66 [68] 53 42 33 p3_0 int0 seg24 67 [69] 54 43 34 p2_7 ki7 seg23 68 [70] 55 44 35 p2_6 ki6 seg22 69 [71] 56 45 36 p2_5 ki5 seg21 70 [72] 57 46 37 p2_4 ki4 seg20 71 [73] 58 p2_3 ki3 seg19 72 [74] 59 p2_2 ki2 seg18 73 [75] 60 p2_1 ki1 seg17 74 [76] 61 p2_0 ki0 seg16 75 [77] p1_7 seg15 76 [78] p1_6 seg14 77 [79] p1_5 seg13 78 [80] p1_4 seg12 79 [81] 62 p1_3 an15 seg11 80 [82] 63 p1_2 an14 seg10 81 [83] 64 p1_1 an13 seg9 82 [84] 65 p1_0 an12 seg8 83 [85] 66 47 38 p0_7 an11 (3) seg7 84 [86] 67 48 39 p0_6 an10 (3) seg6 r8c/l35c group, r8c/l36c group, r8c/l3 8c group, r8c/l3ac group 1. overview r01ds0095ej0101 rev.1.01 page 22 of 72 apr 15, 2011 notes: 1. the pin in parentheses can be assigned by a program. 2. the number in brackets indicates the pin number for the 100p6f package. table 1.13 pin name information by pin number (3) pin number control pin port i/o pin functions for peripheral modules l3ac (note 2) l38c l36c l35c interrupt timer serial interface ssu i 2 c bus a/d converter, d/a converter, comparator b lcd drive control circuit 85 [87] 68 49 40 p0_5 an9 seg5 86 [88] 69 50 41 p0_4 an8 seg4 87 [89] 70 51 42 p0_3 an7 seg3 88 [90] 71 52 43 p0_2 an6 seg2 89 [91] 72 53 44 p0_1 an5 seg1 90 [92] 73 54 45 p0_0 an4 seg0 91 [93] 74 55 46 vl1 92 [94] 75 56 47 vl2 93 [95] 76 57 vl3 94 [96] 77 58 48 p12_3 cl2 95 [97] 78 59 49 p12_2 cl1 96 [98] 79 60 50 vl4 97 [99] p13_7 trgclkb an19 98 [100] p13_6 trgiob an18 99 [1] p13_5 trgclka an17 100 [2] p13_4 trgioa an16 r8c/l35c group, r8c/l36c group, r8c/l3 8c group, r8c/l3ac group 1. overview r01ds0095ej0101 rev.1.01 page 23 of 72 apr 15, 2011 1.5 pin functions tables 1.14 and 1.15 list pin functions for r8c/l3ac group. i: input o: output i/o: input and output note: 1. contact the oscillator manufacturer for oscillation characteristics. table 1.14 pin functions for r8c/l3ac group (1) item pin name i/o type description power supply input vcc, vss ? apply 1.8 v to 5.5 v to the vcc pin. apply 0 v to the vss pin. analog power supply input avcc, avss ? power supply for the a/d converter. connect a capacitor between avcc and avss. reset input reset i driving this pin low resets the mcu. mode mode i connect this pin to vcc via a resistor. power-off mode exit input wkup0 i this pin is provided for input to exit the mode used in power-off mode. connect to vss when not using power-off mode. xin clock input xin i these pins are provid ed for xin clock generation circuit i/o. connect a ceramic oscillator or a crystal oscillator between pins xin and xout. (1) to use an external clock, input it to the xin pin and leave the xout pin open. xin clock output xout o xcin clock input xcin i these pins are pr ovided for xcin clock generation circuit i/o. connect a crystal oscillator between pins xcin and xcout. (1) to use an external clock, input it to the xcin pin and leave the xcout pin open. xcin clock output xcout o int interrupt input int0 to int7 iint interrupt input pins. key input interrupt ki0 to ki7 i key input interrupt input pins timer ra traio i/o timer ra i/o pin trao o timer ra output pin timer rb trbo o timer rb output pin timer rc trcclk i external clock input pin trctrg i external trigger input pin trcioa, trciob, trcioc, trciod i/o timer rc i/o pins timer rd trdioa0, trdioa1, trdiob0, trdiob1, trdioc0, trdioc1, trdiod0, trdiod1 i/o timer rd i/o pins trdclk i external clock input pin timer re treo o divided clock output pin timer rg trgclka, trgclkb i timer rg input pins trgioa, trgiob i/o timer rg i/o pins serial interface clk0, clk1, clk2 i/o transfer clock i/o pins rxd0, rxd1, rxd2 i serial data input pins txd0, txd1, txd2 o serial data output pins cts2 i transmission control input pin rts2 o reception control output pin scl2 i/o i 2 c mode clock i/o pin sda2 i/o i 2 c mode data i/o pin r8c/l35c group, r8c/l36c group, r8c/l3 8c group, r8c/l3ac group 1. overview r01ds0095ej0101 rev.1.01 page 24 of 72 apr 15, 2011 i: input o: output i/o: input and output note: 1. contact the oscillator manufacturer for oscillation characteristics. table 1.15 pin functions for r8c/l3ac group (2) item pin name i/o type description i 2 c bus scl i/o clock i/o pin sda i/o data i/o pin ssu ssi i/o data i/o pin scs i/o chip-select signal i/o pin ssck i/o clock i/o pin sso i/o data i/o pin reference voltage input vref i reference voltage input pin for the a/d converter and the d/a converter a/d converter an0 to an11 i a/d converter analog input pins adtrg i a/d external trigger input pin d/a converter da0, da1 o d/a converter output pins comparator b ivcmp1, ivcmp3 i comparator b analog voltage input pins ivref1, ivref3 i comparator b reference voltage input pins i/o ports p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0, p5_3, p6_0 to p6_7 p7_0 to p7_7, p10_0 to p10_7, p11_0 to p11_7, p12_0 to p12_3, p13_0 to p13_7 i/o cmos i/o ports. each port has an i/o select direction register, allowing each pin in the port to be directed for input or output individually. any port set to input can be set to use a pull-up resistor or not by a program. ports p10_0 to p10_7 and p11_0 to p11_7 can be used as led drive ports. segment output seg0 to seg55 o lcd segment output pins common output com0 to com7 o lcd common output pins voltage multiplier capacity connect pins cl1, cl2 o connect pins for the lcd control voltage multiplier lcd power supply vl1 i/o apply the voltage: 0 vl1 vl2 vl3 vl4. vl1 can be used as the referenc e potential input or output pin when setting the voltage multiplier. vl2 to vl4 i r8c/l35c group, r8c/l36c group, r8 c/l38c group, r8c/l3ac group 2. central processing unit (cpu) r01ds0095ej0101 rev.1.01 page 25 of 72 apr 15, 2011 2. central processi ng unit (cpu) figure 2.1 shows the cpu registers. the cpu contains 13 registers. r0, r1, r2, r3, a0, a1, and fb configure a register bank. there are two sets of register banks. figure 2.1 cpu registers r2 b31 b15 b8b7 b0 data registers (1) address registers (1) r3 r0h (high-order of r0) r2 r3 a0 a1 intbh b15 b19 b0 intbl fb frame base register (1) the 4 high-order bits of intb are intbh and the 16 low-order bits of intb are intbl. interrupt table register b19 b0 usp program counter isp sb user stack pointer interrupt stack pointer static base register pc flg flag register carry flag debug flag zero flag sign flag register bank select flag overflow flag interrupt enable flag stack pointer select flag reserved bit processor interrupt priority level reserved bit c ipl d z s b o i u b15 b0 b15 b0 b15 b0 b8 b7 note: 1. these registers configure a register bank. there are two sets of register banks. r1h (high-order of r1) r0l (low-order of r0) r1l (low-order of r1) r8c/l35c group, r8c/l36c group, r8 c/l38c group, r8c/l3ac group 2. central processing unit (cpu) r01ds0095ej0101 rev.1.01 page 26 of 72 apr 15, 2011 2.1 data registers (r 0, r1, r2, and r3) r0 is a 16-bit register for transfer, ar ithmetic, and logic operations. the same applies to r1 to r3. r0 can be split into high-order bits (r0h) and low-order bits (r0l) to be used separately as 8-bit data registers. r1h and r1l are analogous to r0h and r0l. r2 can be combined with r0 and used as a 32-bit data register (r2r0). r3r1 is analogous to r2r0. 2.2 address registers (a0 and a1) a0 is a 16-bit register for address register indirect addr essing and address register relative addressing. it is also used for transfer, arithmetic, and logic operations. a1 is an alogous to a0. a1 can be comb ined with a0 and as a 32- bit address register (a1a0). 2.3 frame base register (fb) fb is a 16-bit register for fb relative addressing. 2.4 interrupt table register (intb) intb is a 20-bit register that indicates the starti ng address of an interrupt vector table. 2.5 program counter (pc) pc is 20 bits wide and indicates the addres s of the next instruction to be executed. 2.6 user stack pointer (usp) a nd interrupt stack pointer (isp) the stack pointers (sp), usp and isp, are each 16 bits wide. the u flag of flg is used to switch between usp and isp. 2.7 static base register (sb) sb is a 16-bit register for sb relative addressing. 2.8 flag register (flg) flg is an 11-bit register indicating the cpu state. 2.8.1 carry flag (c) the c flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit. 2.8.2 debug flag (d) the d flag is for debugging only. set it to 0. 2.8.3 zero flag (z) the z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0. 2.8.4 sign flag (s) the s flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0. 2.8.5 register bank select flag (b) register bank 0 is selected when the b flag is 0. regi ster bank 1 is selected when this flag is set to 1. 2.8.6 overflow flag (o) the o flag is set to 1 when an operation results in an overflow; otherwise to 0. r8c/l35c group, r8c/l36c group, r8 c/l38c group, r8c/l3ac group 2. central processing unit (cpu) r01ds0095ej0101 rev.1.01 page 27 of 72 apr 15, 2011 2.8.7 interrupt enable flag (i) the i flag enables maskable interrupts. interrupts are disabled when the i flag is set to 0, and are enabled when the i flag is set to 1. the i flag is set to 0 when an interrupt request is acknowledged. 2.8.8 stack pointer select flag (u) isp is selected when the u flag is set to 0; usp is selected when the u flag is set to 1. the u flag is set to 0 when a hardware interrupt requ est is acknowledged or the int instruction of software interrupt numbers 0 to 31 is executed. 2.8.9 processor interrupt priority level (ipl) ipl is 3 bits wide and assigns processor interrupt priority le vels from level 0 to level 7. if a requested interrupt has higher priori ty than ipl, the interrupt is enabled. 2.8.10 reserved bit if necessary, set to 0. when read, the content is undefined. r8c/l35c group, r8c/l36c group, r8c/ l38c group, r8c/l3ac group 3. memory r01ds0095ej0101 rev.1.01 page 28 of 72 apr 15, 2011 3. memory figure 3.1 is a memory map of each group. each gr oup has a 1-mbyte address space from addresses 00000h to fffffh. for example, a 48-kbyte internal rom area is allocated addresses 04000h to 0ffffh. the fixed interrupt vector table is al located addresses 0ffdch to 0ffffh. the starting ad dress of each interrupt routine is stored here. the internal rom (data flash) is a llocated addresses 03000h to 03fffh. the internal ram is allocated higher addresses, beginn ing with address 00400h. for example, a 6-kbyte internal ram area is allocated addresses 00400h to 01bffh. the internal ram is used not only for data storage but also as a stack area when a subroutine is called or when an interrupt request is acknowledged. special function registers (sfrs) ar e allocated addresses 00000h to 002ffh and 02c00h to 02fffh. peripheral function control registers are allocated here. all unalloca ted spaces within the sfrs are reserved and cannot be accessed by users. figure 3.1 memory map 0ffffh 0ffdch notes: 1. data flash indicates bl ock a (1 kbyte), block b (1 kbyte), block c (1 kbyte), and block d (1 kbyte). 2. blank spaces are reserved. no access is allowed. fffffh 0ffffh 0yyyyh 0xxxxh 00400h 002ffh 00000h internal rom (program rom) internal ram sfr (refer to 4. special function registers (sfrs) ) 02fffh 02c00h sfr (refer to 4. special function registers (sfrs) ) zzzzzh internal rom (program rom) 03fffh 03000h internal rom (data flash) (1) 0ffd8h reserved area undefined instruction overflow brk instruction address match single step watchdog timer, oscillation stop detection, voltage monitor address break (reserved) reset part number internal rom internal ram capacity address 0yyyyh capacity address 0xxxxh address zzzzzh 48 kbytes 04000h ? 6 kbytes 01bffh 64 kbytes 04000h 13fffh 8 kbytes 023ffh 96 kbytes 04000h 1bfffh 10 kbytes 02bffh 128 kbytes 04000h 23fffh 10 kbytes 02bffh r5f2l357c***, r5f2l367c***, r5f2l387c***, r5f2l3a7c*** r5f2l358c***, r5f2l368c***, r5f2l388c***, r5f2l3a8c*** r5f2l35ac***, r5f2l36ac***, r5f2l38ac***, r5f2l3aac*** r5f2l35cc***, r5f2l36cc***, r5f2l38cc***, r5f2l3acc*** r8c/l35c group, r8c/l36c group, r8 c/l38c group, r8c/l3ac group 4. special function registers (sfrs) r01ds0095ej0101 rev.1.01 page 29 of 72 apr 15, 2011 4. special function registers (sfrs) an sfr (special function register) is a control register for a peripheral function. tables 4.1 to 4.16 list sfr informations and table 4.17 lists the id code areas and op tion function select area. the description offered in this chapter is based on the r8c/l3ac group. table 4.1 sfr information (1) (1) x: undefined notes: 1. blank spaces are reserved . no access is allowed. 2. the cwr bit in the rstfr register is set to 0 after power-on, voltage monitor 0 reset, or exit from power-off mode. hardware reset, software reset, or watchdog timer reset does not affect this bit. 3. the csproini bit in the ofs register is set to 0. 4. the lvdas bit in the ofs register is set to 1. 5. the lvdas bit in the ofs register is set to 0. address register symbol after reset 0000h 0001h 0002h 0003h 0004h processor mode register 0 pm0 00h 0005h processor mode register 1 pm1 00h 0006h system clock control register 0 cm0 00100000b 0007h system clock control register 1 cm1 00100000b 0008h module standby control register mstcr 00h 0009h system clock control register 3 cm3 00h 000ah protect register prcr 00h 000bh reset source determination register rstfr xxh (2) 000ch oscillation stop detection register ocd 00000100b 000dh watchdog timer reset register wdtr xxh 000eh watchdog timer start register wdts xxh 000fh watchdog timer control register wdtc 00111111b 0010h 0011h 0012h 0013h 0014h 0015h high-speed on-chip oscillator control register 7 fra7 when shipping 0016h 0017h 0018h 0019h 001ah 001bh 001ch count source protection mode register cspr 00h 10000000b (3) 001dh 001eh 001fh 0020h power-off mode control register 0 pomcr0 x0000000b 0021h 0022h 0023h high-speed on-chip oscillator control register 0 fra0 00h 0024h high-speed on-chip oscillator control register 1 fra1 when shipping 0025h high-speed on-chip oscillator control register 2 fra2 00h 0026h on-chip reference voltage control register ocvrefcr 00h 0027h 0028h 0029h high-speed on-chip oscillator control register 4 fra4 when shipping 002ah high-speed on-chip oscillator control register 5 fra5 when shipping 002bh high-speed on-chip oscillator control register 6 fra6 when shipping 002ch 002dh 002eh 002fh high-speed on-chip oscillator control register 3 fra3 when shipping 0030h voltage monitor circuit control register cmpa 00h 0031h voltage monitor circuit edge select register vcac 00h 0032h 0033h voltage detect register 1 vca1 00001000b 0034h voltage detect register 2 vca2 00h (4) 00100000b (5) 0035h 0036h voltage detection 1 level select register vd1ls 00000111b 0037h 0038h voltage monitor 0 circuit control register vw0c 1100x010b (4) 1100x011b (5) 0039h voltage monitor 1 circuit control register vw1c 10001010b r8c/l35c group, r8c/l36c group, r8 c/l38c group, r8c/l3ac group 4. special function registers (sfrs) r01ds0095ej0101 rev.1.01 page 30 of 72 apr 15, 2011 table 4.2 sfr information (2) (1) x: undefined notes: 1. blank spaces are reserved . no access is allowed. 2. selectable by the iicsel bit in the ssuiicsr register. address register symbol after reset 003ah voltage monitor 2 circuit control register vw2c 10000010b 003bh 003ch 003dh 003eh 003fh 0040h 0041h flash memory ready interrupt control register fmrdyic xxxxx000b 0042h 0043h int7 interrupt control register int7ic xx00x000b 0044h int6 interrupt control register int6ic xx00x000b 0045h int5 interrupt control register int5ic xx00x000b 0046h int4 interrupt control register int4ic xx00x000b 0047h timer rc interrupt control register trcic xxxxx000b 0048h timer rd0 interrupt control register trd0ic xxxxx000b 0049h timer rd1 interrupt control register trd1ic xxxxx000b 004ah timer re interrupt control register treic xxxxx000b 004bh uart2 transmit interrupt control register s2tic xxxxx000b 004ch uart2 receive interrupt control register s2ric xxxxx000b 004dh key input interrupt control register kupic xxxxx000b 004eh a/d conversion interrupt control register adic xxxxx000b 004fh ssu interrupt control register / iic bus interrupt control register (2) ssuic/iicic xxxxx000b 0050h 0051h uart0 transmit interrupt control register s0tic xxxxx000b 0052h uart0 receive interrupt control register s0ric xxxxx000b 0053h uart1 transmit interrupt control register s1tic xxxxx000b 0054h uart1 receive interrupt control register s1ric xxxxx000b 0055h int2 interrupt control register int2ic xx00x000b 0056h timer ra interrupt control register traic xxxxx000b 0057h 0058h timer rb interrupt control register trbic xxxxx000b 0059h int1 interrupt control register int1ic xx00x000b 005ah int3 interrupt control register int3ic xx00x000b 005bh 005ch 005dh int0 interrupt control register int0ic xx00x000b 005eh uart2 bus collision detection interrupt control register u2bcnic xxxxx000b 005fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006ah 006bh timer rg interrupt control register trgic xxxxx000b 006ch 006dh 006eh 006fh 0070h 0071h 0072h voltage monitor 1 interrupt control register vcmp1ic xxxxx000b 0073h voltage monitor 2 interrupt control register vcmp2ic xxxxx000b 0074h 0075h 0076h 0077h 0078h 0079h 007ah 007bh 007ch 007dh 007eh 007fh r8c/l35c group, r8c/l36c group, r8 c/l38c group, r8c/l3ac group 4. special function registers (sfrs) r01ds0095ej0101 rev.1.01 page 31 of 72 apr 15, 2011 table 4.3 sfr information (3) (1) x: undefined note: 1. blank spaces are reserved . no access is allowed. address register symbol after reset 0080h dtc activation control register dtctl 00h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h dtc activation enable register 0 dtcen0 00h 0089h dtc activation enable register 1 dtcen1 00h 008ah dtc activation enable register 2 dtcen2 00h 008bh dtc activation enable register 3 dtcen3 00h 008ch dtc activation enable register 4 dtcen4 00h 008dh dtc activation enable register 5 dtcen5 00h 008eh dtc activation enable register 6 dtcen6 00h 008fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009ah 009bh 009ch 009dh 009eh 009fh 00a0h uart0 transmit/receive mode register u0mr 00h 00a1h uart0 bit rate register u0brg xxh 00a2h uart0 transmit buffer register u0tb xxh 00a3h xxh 00a4h uart0 transmit/receive control register 0 u0c0 00001000b 00a5h uart0 transmit/receive control register 1 u0c1 00000010b 00a6h uart0 receive buffer register u0rb xxh 00a7h xxh 00a8h uart2 transmit/receive mode register u2mr 00h 00a9h uart2 bit rate register u2brg xxh 00aah uart2 transmit buffer register u2tb xxh 00abh xxh 00ach uart2 transmit/receive control register 0 u2c0 00001000b 00adh uart2 transmit/receive control register 1 u2c1 00000010b 00aeh uart2 receive buffer register u2rb xxh 00afh xxh 00b0h uart2 digital filter function select register urxdf 00h 00b1h 00b2h 00b3h 00b4h 00b5h 00b6h 00b7h 00b8h 00b9h 00bah 00bbh uart2 special mode register 5 u2smr5 00h 00bch uart2 special mode register 4 u2smr4 00h 00bdh uart2 special mode register 3 u2smr3 000x0x0xb 00beh uart2 special mode register 2 u2smr2 x0000000b 00bfh uart2 special mode register u2smr x0000000b r8c/l35c group, r8c/l36c group, r8 c/l38c group, r8c/l3ac group 4. special function registers (sfrs) r01ds0095ej0101 rev.1.01 page 32 of 72 apr 15, 2011 table 4.4 sfr information (4) (1) x: undefined note: 1. blank spaces are reserved . no access is allowed. address register symbol after reset 00c0h a/d register 0 ad0 xxh 000000xxb 00c1h 00c2h a/d register 1 ad1 xxh 00c3h 000000xxb 00c4h a/d register 2 ad2 xxh 00c5h 000000xxb 00c6h a/d register 3 ad3 xxh 00c7h 000000xxb 00c8h a/d register 4 ad4 xxh 00c9h 000000xxb 00cah a/d register 5 ad5 xxh 00cbh 000000xxb 00cch a/d register 6 ad6 xxh 00cdh 000000xxb 00ceh a/d register 7 ad7 xxh 00cfh 000000xxb 00d0h 00d1h 00d2h 00d3h 00d4h a/d mode register admod 00h 00d5h a/d input select register adinsel 11000000b 00d6h a/d control register 0 adcon0 00h 00d7h a/d control register 1 adcon1 00h 00d8h d/a 0 register da0 00h 00d9h d/a 1 register da1 00h 00dah 00dbh 00dch d/a control register dacon 00h 00ddh 00deh 00dfh 00e0h port p0 register p0 xxh 00e1h port p1 register p1 xxh 00e2h port p0 direction register pd0 00h 00e3h port p1 direction register pd1 00h 00e4h port p2 register p2 xxh 00e5h port p3 register p3 xxh 00e6h port p2 direction register pd2 00h 00e7h port p3 direction register pd3 00h 00e8h port p4 register p4 xxh 00e9h port p5 register p5 xxh 00eah port p4 direction register pd4 00h 00ebh port p5 direction register pd5 00h 00ech port p6 register p6 xxh 00edh port p7 register p7 xxh 00eeh port p6 direction register pd6 00h 00efh port p7 direction register pd7 00h 00f0h 00f1h 00f2h 00f3h 00f4h port p10 register p10 xxh 00f5h port p11 register p11 xxh 00f6h port p10 direction register pd10 00h 00f7h port p11 direction register pd11 00h 00f8h port p12 register p12 xxh 00f9h port p13 register p13 xxh 00fah port p12 direction register pd12 00h 00fbh port p13 direction register pd13 00h 00fch 00fdh 00feh 00ffh r8c/l35c group, r8c/l36c group, r8 c/l38c group, r8c/l3ac group 4. special function registers (sfrs) r01ds0095ej0101 rev.1.01 page 33 of 72 apr 15, 2011 table 4.5 sfr information (5) (1) x: undefined note: 1. blank spaces are reserved . no access is allowed. address register symbol after reset 0100h timer ra control register tracr 00h 0101h timer ra i/o control register traioc 00h 0102h timer ra mode register tramr 00h 0103h timer ra prescaler register trapre ffh 0104h timer ra register tra ffh 0105h lin control register 2 lincr2 00h 0106h lin control register lincr 00h 0107h lin status register linst 00h 0108h timer rb control register trbcr 00h 0109h timer rb one-shot control register trbocr 00h 010ah timer rb i/o control register trbioc 00h 010bh timer rb mode register trbmr 00h 010ch timer rb prescaler register trbpre ffh 010dh timer rb secondary register trbsc ffh 010eh timer rb primary register trbpr ffh 010fh 0110h 0111h 0112h 0113h 0114h 0115h 0116h 0117h 0118h timer re second data register / timer re counter data register tresec xxh 0119h timer re minute data register / timer re compare data register tremin xxh 011ah timer re hour data register trehr xxh 011bh timer re day of week data register trewk xxh 011ch timer re control register 1 trecr1 xxxxx0xxb 011dh timer re control register 2 trecr2 xxh 011eh timer re count source select register trecsr 00001000b 011fh 0120h timer rc mode register trcmr 01001000b 0121h timer rc control register 1 trccr1 00h 0122h timer rc interrupt enable register trcier 01110000b 0123h timer rc status register trcsr 01110000b 0124h timer rc i/o control register 0 trcior0 10001000b 0125h timer rc i/o control register 1 trcior1 10001000b 0126h timer rc counter trc 00h 0127h 00h 0128h timer rc general register a trcgra ffh 0129h ffh 012ah timer rc general register b trcgrb ffh 012bh ffh 012ch timer rc general register c trcgrc ffh 012dh ffh 012eh timer rc general register d trcgrd ffh 012fh ffh 0130h timer rc control register 2 trccr2 00011000b 0131h timer rc digital filter function select register trcdf 00h 0132h timer rc output master enable register trcoer 0 1111111b 0133h timer rc trigger control register trcadcr 00h 0134h 0135h timer rd control expansion register trdecr 00h 0136h timer rd trigger control register trdadcr 00h 0137h timer rd start register trdstr 11111100b 0138h timer rd mode register trdmr 00001110b 0139h timer rd pwm mode register trdpmr 10001000b 013ah timer rd function control register trdfcr 10000000b 013bh timer rd output master enable register 1 trdoer1 ffh 013ch timer rd output master enable register 2 trdoer2 0 1111111b 013dh timer rd output control register trdocr 00h 013eh timer rd digital filter function select register 0 trddf0 00h 013fh timer rd digital filter function select register 1 trddf1 00h r8c/l35c group, r8c/l36c group, r8 c/l38c group, r8c/l3ac group 4. special function registers (sfrs) r01ds0095ej0101 rev.1.01 page 34 of 72 apr 15, 2011 table 4.6 sfr information (6) (1) x: undefined note: 1. blank spaces are reserved . no access is allowed. address register symbol after reset 0140h timer rd control register 0 trdcr0 00h 0141h timer rd i/o control register a0 trdiora0 10001000b 0142h timer rd i/o control register c0 trdiorc0 10001000b 0143h timer rd status register 0 trdsr0 11100000b 0144h timer rd interrupt enable register 0 trdier0 11100000b 0145h timer rd pwm mode output level control register 0 trdpocr0 1111 1000b 0146h timer rd counter 0 trd0 00h 0147h 00h 0148h timer rd general register a0 trdgra0 ffh 0149h ffh 014ah timer rd general register b0 trdgrb0 ffh 014bh ffh 014ch timer rd general register c0 trdgrc0 ffh 014dh ffh 014eh timer rd general register d0 trdgrd0 ffh 014fh ffh 0150h timer rd control register 1 trdcr1 00h 0151h timer rd i/o control register a1 trdiora1 10001000b 0152h timer rd i/o control register c1 trdiorc1 10001000b 0153h timer rd status register 1 trdsr1 11000000b 0154h timer rd interrupt enable register 1 trdier1 11100000b 0155h timer rd pwm mode output level control register 1 trdpocr1 1111 1000b 0156h timer rd counter 1 trd1 00h 0157h 00h 0158h timer rd general register a1 trdgra1 ffh 0159h ffh 015ah timer rd general register b1 trdgrb1 ffh 015bh ffh 015ch timer rd general register c1 trdgrc1 ffh 015dh ffh 015eh timer rd general register d1 trdgrd1 ffh 015fh ffh 0160h uart1 transmit/receive mode register u1mr 00h 0161h uart1 bit rate register u1brg xxh 0162h uart1 transmit buffer register u1tb xxh 0163h xxh 0164h uart1 transmit/receive control register 0 u1c0 00001000b 0165h uart1 transmit/receive control register 1 u1c1 00000010b 0166h uart1 receive buffer register u1rb xxh 0167h xxh 0168h 0169h 016ah 016bh 016ch 016dh 016eh 016fh 0170h timer rg mode register trgmr 01000000b 0171h timer rg count control register trgcntc 00h 0172h timer rg control register trgcr 10000000b 0173h timer rg interrupt enable register trgier 11110000b 0174h timer rg status register trgsr 11100000b 0175h timer rg i/o control register trgior 00h 0176h timer rg counter trg 00h 0177h 00h 0178h timer rg general register a trggra ffh 0179h ffh 017ah timer rg general register b trggrb ffh 017bh ffh 017ch timer rg general register c trggrc ffh 017dh ffh 017eh timer rg general register d trggrd ffh 017fh ffh r8c/l35c group, r8c/l36c group, r8 c/l38c group, r8c/l3ac group 4. special function registers (sfrs) r01ds0095ej0101 rev.1.01 page 35 of 72 apr 15, 2011 table 4.7 sfr information (7) (1) x: undefined notes: 1. blank spaces are reserved . no access is allowed. 2. selectable by the iicsel bit in the ssuiicsr register. address register symbol after reset 0180h timer ra pin select register trasr 00h 0181h timer rb/rc pin select register trbrcsr 00h 0182h timer rc pin select register 0 trcpsr0 00h 0183h timer rc pin select register 1 trcpsr1 00h 0184h timer rd pin select register 0 trdpsr0 00h 0185h timer rd pin select register 1 trdpsr1 00h 0186h 0187h timer rg pin select register trgpsr 00h 0188h uart0 pin select register u0sr 00h 0189h uart1 pin select register u1sr 00h 018ah uart2 pin select register 0 u2sr0 00h 018bh uart2 pin select register 1 u2sr1 00h 018ch ssu/iic pin select register ssuiicsr 00h 018dh key input pin select register kisr 00h 018eh int interrupt input pin select register intsr 00h 018fh i/o function pin select register pinsr 00h 0190h 0191h 0192h 0193h ss bit counter register ssbr 1111 1000b 0194h ss transmit data register l / iic bus transmit data register (2) sstdr/icdrt ffh 0195h ss transmit data register h (2) sstdrh ffh 0196h ss receive data register l / iic bus receive data register (2) ssrdr/icdrr ffh 0197h ss receive data register h (2) ssrdrh ffh 0198h ss control register h / iic bus control register 1 (2) sscrh/iccr1 00h 0199h ss control register l / iic bus control register 2 (2) sscrl/iccr2 0 1111101b 019ah ss mode register / iic bus mode register (2) ssmr/icmr 00010000b/00011000b 019bh ss enable register / iic bus interrupt enable register (2) sser/icier 00h 019ch ss status register / iic bus status register (2) sssr/icsr 00h/0000x000b 019dh ss mode register 2 / slave address register (2) ssmr2/sar 00h 019eh 019fh 01a0h 01a1h 01a2h 01a3h 01a4h 01a5h 01a6h 01a7h 01a8h 01a9h 01aah 01abh 01ach 01adh 01aeh 01afh 01b0h 01b1h 01b2h flash memory status register fst 10000x00b 01b3h 01b4h flash memory control register 0 fmr0 00h 01b5h flash memory control register 1 fmr1 00h 01b6h flash memory control register 2 fmr2 00h 01b7h 01b8h 01b9h 01bah 01bbh 01bch 01bdh 01beh 01bfh r8c/l35c group, r8c/l36c group, r8 c/l38c group, r8c/l3ac group 4. special function registers (sfrs) r01ds0095ej0101 rev.1.01 page 36 of 72 apr 15, 2011 table 4.8 sfr information (8) (1) x: undefined note: 1. blank spaces are reserved . no access is allowed. address register symbol after reset 01c0h address match interrupt register 0 rmad0 xxh xxh 0000xxxxb 01c1h 01c2h 01c3h address match interrupt enable register 0 aier0 00h 01c4h address match interrupt register 1 rmad1 xxh 01c5h xxh 01c6h 0000xxxxb 01c7h address match interrupt enable register 1 aier1 00h 01c8h 01c9h 01cah 01cbh 01cch 01cdh 01ceh 01cfh 01d0h 01d1h 01d2h 01d3h 01d4h 01d5h 01d6h 01d7h 01d8h 01d9h 01dah 01dbh 01dch 01ddh 01deh 01dfh 01e0h port p0 pull-up control register p0pur 00h 01e1h port p1 pull-up control register p1pur 00h 01e2h port p2 pull-up control register p2pur 00h 01e3h port p3 pull-up control register p3pur 00h 01e4h port p4 pull-up control register p4pur 00h 01e5h port p5 pull-up control register p5pur 00h 01e6h port p6 pull-up control register p6pur 00h 01e7h port p7 pull-up control register p7pur 00h 01e8h 01e9h 01eah port 10 pull-up control register p10pur 00h 01ebh port 11 pull-up control register p11pur 00h 01ech port 12 pull-up control register p12pur 00h 01edh port 13 pull-up control register p13pur 00h 01eeh 01efh 01f0h port p10 drive capacity control register p10drr 00h 01f1h port p11 drive capacity control register p11drr 00h 01f2h 01f3h 01f4h 01f5h input threshold control register 0 vlt0 00h 01f6h input threshold control register 1 vlt1 00h 01f7h input threshold control register 2 vlt2 00h 01f8h comparator b control register 0 intcmp 00h 01f9h 01fah external input enable register 0 inten 00h 01fbh external input enable register 1 inten1 00h 01fch int input filter select register 0 intf 00h 01fdh int input filter select register 1 intf1 00h 01feh key input enable register 0 kien 00h 01ffh key input enable register 1 kien1 00h r8c/l35c group, r8c/l36c group, r8 c/l38c group, r8c/l3ac group 4. special function registers (sfrs) r01ds0095ej0101 rev.1.01 page 37 of 72 apr 15, 2011 table 4.9 sfr information (9) (1) x: undefined note: 1. blank spaces are reserved . no access is allowed. address register symbol after reset 0200h lcd control register lcr0 00h 0201h lcd bias control register lcr1 00h 0202h lcd display control register lcr2 x0000000b 0203h lcd clock control register lcr3 00h 0204h 0205h 0206h lcd port select register 0 lse0 00h 0207h lcd port select register 1 lse1 00h 0208h lcd port select register 2 lse2 00h 0209h lcd port select register 3 lse3 00h 020ah lcd port select register 4 lse4 00h 020bh lcd port select register 5 lse5 00h 020ch lcd port select register 6 lse6 00h 020dh lcd port select register 7 lse7 00h 020eh 020fh 0210h lcd display data register lra0l xxh 0211h lra1l xxh 0212h lra2l xxh 0213h lra3l xxh 0214h lra4l xxh 0215h lra5l xxh 0216h lra6l xxh 0217h lra7l xxh 0218h lra8l xxh 0219h lra9l xxh 021ah lra10l xxh 021bh lra11l xxh 021ch lra12l xxh 021dh lra13l xxh 021eh lra14l xxh 021fh lra15l xxh 0220h lra16l xxh 0221h lra17l xxh 0222h lra18l xxh 0223h lra19l xxh 0224h lra20l xxh 0225h lra21l xxh 0226h lra22l xxh 0227h lra23l xxh 0228h lra24l xxh 0229h lra25l xxh 022ah lra26l xxh 022bh lra27l xxh 022ch lra28l xxh 022dh lra29l xxh 022eh lra30l xxh 022fh lra31l xxh 0230h lra32l xxh 0231h lra33l xxh 0232h lra34l xxh 0233h lra35l xxh 0234h lra36l xxh 0235h lra37l xxh 0236h lra38l xxh 0237h lra39l xxh 0238h lra40l xxh 0239h lra41l xxh 023ah lra42l xxh 023bh lra43l xxh 023ch lra44l xxh 023dh lra45l xxh 023eh lra46l xxh 023fh lra47l xxh r8c/l35c group, r8c/l36c group, r8 c/l38c group, r8c/l3ac group 4. special function registers (sfrs) r01ds0095ej0101 rev.1.01 page 38 of 72 apr 15, 2011 table 4.10 sfr information (10) (1) x: undefined note: 1. blank spaces are reserved . no access is allowed. address register symbol after reset 0240h lcd display data register lra48l xxh 0241h lra49l xxh 0242h lra50l xxh 0243h lra51l xxh 0244h lra52l xxh 0245h lra53l xxh 0246h lra54l xxh 0247h lra55l xxh 0248h 0249h 024ah 024bh 024ch 024dh 024eh 024fh 0250h 0251h 0252h 0253h 0254h 0255h 0256h 0257h 0258h 0259h 025ah 025bh 025ch 025dh 025eh 025fh 0260h 0261h 0262h 0263h 0264h 0265h 0266h 0267h 0268h 0269h 026ah 026bh 026ch 026dh 026eh 026fh 0270h lcd display control data register lra0h xxh 0271h lra1h xxh 0272h lra2h xxh 0273h lra3h xxh 0274h lra4h xxh 0275h lra5h xxh 0276h lra6h xxh 0277h lra7h xxh 0278h lra8h xxh 0279h lra9h xxh 027ah lra10h xxh 027bh lra11h xxh 027ch lra12h xxh 027dh lra13h xxh 027eh lra14h xxh 027fh lra15h xxh r8c/l35c group, r8c/l36c group, r8 c/l38c group, r8c/l3ac group 4. special function registers (sfrs) r01ds0095ej0101 rev.1.01 page 39 of 72 apr 15, 2011 table 4.11 sfr information (11) (1) x: undefined note: 1. blank spaces are reserved . no access is allowed. address register symbol after reset 0280h lcd display control data register lra16h xxh 0281h lra17h xxh 0282h lra18h xxh 0283h lra19h xxh 0284h lra20h xxh 0285h lra21h xxh 0286h lra22h xxh 0287h lra23h xxh 0288h lra24h xxh 0289h lra25h xxh 028ah lra26h xxh 028bh lra27h xxh 028ch lra28h xxh 028dh lra29h xxh 028eh lra30h xxh 028fh lra31h xxh 0290h lra32h xxh 0291h lra33h xxh 0292h lra34h xxh 0293h lra35h xxh 0294h lra36h xxh 0295h lra37h xxh 0296h lra38h xxh 0297h lra39h xxh 0298h lra40h xxh 0299h lra41h xxh 029ah lra42h xxh 029bh lra43h xxh 029ch lra44h xxh 029dh lra45h xxh 029eh lra46h xxh 029fh lra47h xxh 02a0h lra48h xxh 02a1h lra49h xxh 02a2h lra50h xxh 02a3h lra51h xxh 02a4h lra52h xxh 02a5h lra53h xxh 02a6h lra54h xxh 02a7h lra55h xxh 02a8h 02a9h 02aah 02abh 02ach 02adh 02aeh 02afh 02b0h 02b1h 02b2h 02b3h 02b4h 02b5h 02b6h 02b7h 02b8h 02b9h 02bah 02bbh 02bch 02bdh 02beh 02bfh r8c/l35c group, r8c/l36c group, r8 c/l38c group, r8c/l3ac group 4. special function registers (sfrs) r01ds0095ej0101 rev.1.01 page 40 of 72 apr 15, 2011 table 4.12 sfr information (12) (1) x: undefined note: 1. blank spaces are reserved . no access is allowed. address register symbol after reset 02c0h 02c1h 02c2h 02c3h 02c4h 02c5h 02c6h 02c7h 02c8h 02c9h 02cah 02cbh 02cch 02cdh 02ceh 02cfh 02d0h 02d1h 02d2h 02d3h 02d4h 02d5h 02d6h 02d7h 02d8h 02d9h 02dah 02dbh 02dch 02ddh 02deh 02dfh 02e0h 02e1h 02e2h 02e3h 02e4h 02e5h 02e6h 02e7h 02e8h 02e9h 02eah 02ebh 02ech 02edh 02eeh 02efh 02f0h 02f1h 02f2h 02f3h 02f4h 02f5h 02f6h 02f7h 02f8h 02f9h 02fah 02fbh 02fch 02fdh 02feh 02ffh r8c/l35c group, r8c/l36c group, r8 c/l38c group, r8c/l3ac group 4. special function registers (sfrs) r01ds0095ej0101 rev.1.01 page 41 of 72 apr 15, 2011 table 4.13 sfr information (13) (1) x: undefined note: 1. blank spaces are reserved . no access is allowed. address register symbol after reset 2c00h dtc transfer vector area xxh 2c01h dtc transfer vector area xxh 2c02h dtc transfer vector area xxh 2c03h dtc transfer vector area xxh 2c04h dtc transfer vector area xxh 2c05h dtc transfer vector area xxh 2c06h dtc transfer vector area xxh 2c07h dtc transfer vector area xxh 2c08h dtc transfer vector area xxh 2c09h dtc transfer vector area xxh 2c0ah dtc transfer vector area xxh : dtc transfer vector area xxh : dtc transfer vector area xxh 2c3ah dtc transfer vector area xxh 2c3bh dtc transfer vector area xxh 2c3ch dtc transfer vector area xxh 2c3dh dtc transfer vector area xxh 2c3eh dtc transfer vector area xxh 2c3fh dtc transfer vector area xxh 2c40h dtc control data 0 dtcd0 xxh 2c41h xxh 2c42h xxh 2c43h xxh 2c44h xxh 2c45h xxh 2c46h xxh 2c47h xxh 2c48h dtc control data 1 dtcd1 xxh 2c49h xxh 2c4ah xxh 2c4bh xxh 2c4ch xxh 2c4dh xxh 2c4eh xxh 2c4fh xxh 2c50h dtc control data 2 dtcd2 xxh 2c51h xxh 2c52h xxh 2c53h xxh 2c54h xxh 2c55h xxh 2c56h xxh 2c57h xxh 2c58h dtc control data 3 dtcd3 xxh 2c59h xxh 2c5ah xxh 2c5bh xxh 2c5ch xxh 2c5dh xxh 2c5eh xxh 2c5fh xxh 2c60h dtc control data 4 dtcd4 xxh 2c61h xxh 2c62h xxh 2c63h xxh 2c64h xxh 2c65h xxh 2c66h xxh 2c67h xxh 2c68h dtc control data 5 dtcd5 xxh 2c69h xxh 2c6ah xxh 2c6bh xxh 2c6ch xxh 2c6dh xxh 2c6eh xxh 2c6fh xxh r8c/l35c group, r8c/l36c group, r8 c/l38c group, r8c/l3ac group 4. special function registers (sfrs) r01ds0095ej0101 rev.1.01 page 42 of 72 apr 15, 2011 table 4.14 sfr information (14) (1) x: undefined note: 1. blank spaces are reserved . no access is allowed. address register symbol after reset 2c70h dtc control data 6 dtcd6 xxh 2c71h xxh 2c72h xxh 2c73h xxh 2c74h xxh 2c75h xxh 2c76h xxh 2c77h xxh 2c78h dtc control data 7 dtcd7 xxh 2c79h xxh 2c7ah xxh 2c7bh xxh 2c7ch xxh 2c7dh xxh 2c7eh xxh 2c7fh xxh 2c80h dtc control data 8 dtcd8 xxh 2c81h xxh 2c82h xxh 2c83h xxh 2c84h xxh 2c85h xxh 2c86h xxh 2c87h xxh 2c88h dtc control data 9 dtcd9 xxh 2c89h xxh 2c8ah xxh 2c8bh xxh 2c8ch xxh 2c8dh xxh 2c8eh xxh 2c8fh xxh 2c90h dtc control data 10 dtcd10 xxh 2c91h xxh 2c92h xxh 2c93h xxh 2c94h xxh 2c95h xxh 2c96h xxh 2c97h xxh 2c98h dtc control data 11 dtcd11 xxh 2c99h xxh 2c9ah xxh 2c9bh xxh 2c9ch xxh 2c9dh xxh 2c9eh xxh 2c9fh xxh 2ca0h dtc control data 12 dtcd12 xxh 2ca1h xxh 2ca2h xxh 2ca3h xxh 2ca4h xxh 2ca5h xxh 2ca6h xxh 2ca7h xxh 2ca8h dtc control data 13 dtcd13 xxh 2ca9h xxh 2caah xxh 2cabh xxh 2cach xxh 2cadh xxh 2caeh xxh 2cafh xxh r8c/l35c group, r8c/l36c group, r8 c/l38c group, r8c/l3ac group 4. special function registers (sfrs) r01ds0095ej0101 rev.1.01 page 43 of 72 apr 15, 2011 table 4.15 sfr information (15) (1) x: undefined note: 1. blank spaces are reserved . no access is allowed. address register symbol after reset 2cb0h dtc control data 14 dtcd14 xxh 2cb1h xxh 2cb2h xxh 2cb3h xxh 2cb4h xxh 2cb5h xxh 2cb6h xxh 2cb7h xxh 2cb8h dtc control data 15 dtcd15 xxh 2cb9h xxh 2cbah xxh 2cbbh xxh 2cbch xxh 2cbdh xxh 2cbeh xxh 2cbfh xxh 2cc0h dtc control data 16 dtcd16 xxh 2cc1h xxh 2cc2h xxh 2cc3h xxh 2cc4h xxh 2cc5h xxh 2cc6h xxh 2cc7h xxh 2cc8h dtc control data 17 dtcd17 xxh 2cc9h xxh 2ccah xxh 2ccbh xxh 2ccch xxh 2ccdh xxh 2cceh xxh 2ccfh xxh 2cd0h dtc control data 18 dtcd18 xxh 2cd1h xxh 2cd2h xxh 2cd3h xxh 2cd4h xxh 2cd5h xxh 2cd6h xxh 2cd7h xxh 2cd8h dtc control data 19 dtcd19 xxh 2cd9h xxh 2cdah xxh 2cdbh xxh 2cdch xxh 2cddh xxh 2cdeh xxh 2cdfh xxh 2ce0h dtc control data 20 dtcd20 xxh 2ce1h xxh 2ce2h xxh 2ce3h xxh 2ce4h xxh 2ce5h xxh 2ce6h xxh 2ce7h xxh 2ce8h dtc control data 21 dtcd21 xxh 2ce9h xxh 2ceah xxh 2cebh xxh 2cech xxh 2cedh xxh 2ceeh xxh 2cefh xxh r8c/l35c group, r8c/l36c group, r8 c/l38c group, r8c/l3ac group 4. special function registers (sfrs) r01ds0095ej0101 rev.1.01 page 44 of 72 apr 15, 2011 table 4.16 sfr information (16) (1) x: undefined note: 1. blank spaces are reserved . no access is allowed. table 4.17 id code areas and option function select area notes: 1. the option function select area is allocated in the flash memory , not in the sfrs. set appropriate values as rom data by a pr ogram. do not write additions to the option function select area. if the block including the option function select area is erased, th e option function select area is set to ffh. when blank products are shipped, the option function select area is set to ffh. it is set to the written value after written by the user. when factory-programming products are shipped, the value of the option function select area is t he value programmed by the user . 2. the id code areas are allocated in the flash memory, not in the sfrs. set appropriate values as rom data by a program. do not write additions to the id code areas. if the block includ ing the id code areas is erased, the id code areas are set to f fh. when blank products are shipped, the id code areas are set to ffh. they are set to the written value after written by the user. when factory-programming products are shipped, the value of the id code areas is the value programmed by the user. address register symbol after reset 2cf0h dtc control data 22 dtcd22 xxh 2cf1h xxh 2cf2h xxh 2cf3h xxh 2cf4h xxh 2cf5h xxh 2cf6h xxh 2cf7h xxh 2cf8h dtc control data 23 dtcd23 xxh 2cf9h xxh 2cfah xxh 2cfbh xxh 2cfch xxh 2cfdh xxh 2cfeh xxh 2cffh xxh 2d00h : 2fffh address area name symbol after reset : ffdbh option function select register 2 ofs2 (note 1) : ffdfh id1 (note 2) : ffe3h id2 (note 2) : ffebh id3 (note 2) : ffefh id4 (note 2) : fff3h id5 (note 2) : fff7h id6 (note 2) : fffbh id7 (note 2) : ffffh option function select register ofs (note 1) r8c/l35c group, r8c/l36c group, r8c/l38c group, r8c/l3ac group 5. electrical characteristics r01ds0095ej0101 rev.1.01 page 45 of 72 apr 15, 2011 5. electrical characteristics 5.1 absolute maximum ratings notes: 1. for the register settings for each operation, refer to 7. i/o ports and 9. clock generation circuit in the user?s manual: hardware. 2. the vl1 voltage should be vcc or below. table 5.1 absolute maximum ratings symbol parameter condition rated value unit v cc /av cc supply voltage ? 0.3 to 6.5 v v i input voltage xin xin-x out oscillation on (oscillation buffer on) (1) ? 0.3 to 1.65 v xin xin-xout oscillation on (oscillation buffer off) (1) ? 0.3 to v cc + 0.3 v vl1 ? 0.3 to vl2 v vl2 r8c/l35c vl1 to vl4 v r8c/l36c, r8c/l38c, r8c/l3ac vl1 to vl3 v vl3 vl2 to vl4 v vl4 vl3 to 6.5 v other pins ? 0.3 to v cc + 0.3 v v o output voltage xout xin-xout oscillation on (oscillation buffer on) (1) ? 0.3 to 1.65 v xout xin-xout oscillation on (oscillation buffer off) (1) ? 0.3 to v cc + 0.3 v vl1 ? 0.3 to vl2 (2) v vl2 r8c/l35c vl1 to vl4 v r8c/l36c, r8c/l38c, r8c/l3ac vl1 to vl3 v vl3 vl2 to vl4 v vl4 ? 0.3 to 6.5 v cl1, cl2 ? 0.3 to 6.5 v com0 to com7 ? 0.3 to vl4 v seg0 to seg55 ? 0.3 to vl4 v other pins ? 0.3 to v cc + 0.3 v p d power dissipation ? 40 c t opr 85 c 500 mw t opr operating ambient temperature ? 20 to 85 (n version) / ? 40 to 85 (d version) c t stg storage temperature ? 65 to 150 c r8c/l35c group, r8c/l36c group, r8c/l38c group, r8c/l3ac group 5. electrical characteristics r01ds0095ej0101 rev.1.01 page 46 of 72 apr 15, 2011 5.2 recommended operating conditions notes: 1. the average output current indicates the average value of current measured during 100 ms. 2. this applies when the drive capacity of th e output transistor is set to high by registers p10drr and p11drr. when the drive capacity is set to low, the value of any other pin applies. 3. foco40m can be used as the count source for timer rc, timer rd, or timer rg in the range of v cc = 2.7 v to 5.5v. table 5.2 recommended operating conditions (v cc = 1.8 to 5.5 v and t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter conditions standard unit min. typ. max. v cc /av cc supply voltage 1.8 ? 5.5 v v ss /av ss supply voltage ?0?v v ih input ?h? voltage other than cmos input 4.0 v v cc 5.5 v 0.8 v cc ?v cc v 2.7 v v cc < 4.0 v 0.8 v cc ?v cc v 1.8 v v cc < 2.7 v 0.9 v cc ?v cc v cmos input input level switching function (i/o port) input level selection : 0.35 v cc 4.0 v v cc 5.5 v 0.5 v cc ?v cc v 2.7 v v cc < 4.0 v 0.55 v cc ?v cc v 1.8 v v cc < 2.7 v 0.65 v cc ?v cc v input level selection : 0.5 v cc 4.0 v v cc 5.5 v 0.65 v cc ?v cc v 2.7 v v cc < 4.0 v 0.7 v cc ?v cc v 1.8 v v cc < 2.7 v 0.8 v cc ?v cc v input level selection : 0.7 v cc 4.0 v v cc 5.5 v 0.85 v cc ?v cc v 2.7 v v cc < 4.0 v 0.85 v cc ?v cc v 1.8 v v cc < 2.7 v 0.85 v cc ?v cc v v il input ?l? voltage other than cmos input 4.0 v v cc 5.5 v 0 ? 0.2 v cc v 2.7 v v cc < 4.0 v 0 ? 0.2 v cc v 1.8 v v cc < 2.7 v 0 ? 0.05 v cc v cmos input input level switching function (i/o port) input level selection : 0.35 v cc 4.0 v v cc 5.5 v 0 ? 0.2 v cc v 2.7 v v cc < 4.0 v 0 ? 0.2 v cc v 1.8 v v cc < 2.7 v 0 ? 0.2 v cc v input level selection : 0.5 v cc 4.0 v v cc 5.5 v 0 ? 0.4 v cc v 2.7 v v cc < 4.0 v 0 ? 0.3 v cc v 1.8 v v cc < 2.7 v 0 ? 0.2 v cc v input level selection : 0.7 v cc 4.0 v v cc 5.5 v 0 ? 0.55 v cc v 2.7 v v cc < 4.0 v 0 ? 0.45 v cc v 1.8 v v cc < 2.7 v 0 ? 0.35 v cc v i oh(sum) peak sum output ?h? current sum of all pins i oh(peak) ?? ? 160 ma i oh(sum) average sum output ?h? current sum of all pins i oh(avg) ?? ? 80 ma i oh(peak) peak output ?h? current port p10, p11 (2) ?? ? 40 ma other pins ? ? ? 10 ma i oh(avg) average output ?h? current (1) port p10, p11 (2) ?? ? 20 ma other pins ? ? ? 5ma i ol(sum) peak sum output ?l? current sum of all pins i ol(peak) ? ? 160 ma i ol(sum) average sum output ?l? current sum of all pins i ol(avg) ??80ma i ol(peak) peak output ?l? current port p10, p11 (2) ??40ma other pins ? ? 10 ma i ol(avg) average output ?l? current (1) port p10, p11 (2) ??20ma other pins ? ? 5 ma f (xin) xin clock input oscillation frequency 2.7 v v cc 5.5 v ? ? 20 mhz 1.8 v v cc < 2.7 v ? ? 5 mhz f (xcin) xcin clock input oscillation frequency 1.8 v v cc 5.5 v ? 32.768 50 khz foco40m when used as the count source for timer rc, timer rd, or timer rg (3) 2.7 v v cc 5.5 v 32 ? 40 mhz foco-f foco-f frequency 2.7 v v cc 5.5 v ? ? 20 mhz 1.8 v v cc < 2.7 v ? ? 5 mhz ? system clock frequency 2.7 v v cc 5.5 v ? ? 20 mhz 1.8 v v cc < 2.7 v ? ? 5 mhz f (bclk) cpu clock frequency 2.7 v v cc 5.5 v ? ? 20 mhz 1.8 v v cc < 2.7 v ? ? 5 mhz r8c/l35c group, r8c/l36c group, r8c/l38c group, r8c/l3ac group 5. electrical characteristics r01ds0095ej0101 rev.1.01 page 47 of 72 apr 15, 2011 figure 5.1 ports p0 to p4, p5_0 to p5_3, p6, p7 , p10, p11, p12_0 to p12_3, and p13 timing measurement circuit 30 pf p0 p1 p2 p3 p4 p5_0 to p5_3 p6 p7 p10 p11 p12_0 to p12_3 p13 r8c/l35c group, r8c/l36c group, r8c/l38c group, r8c/l3ac group 5. electrical characteristics r01ds0095ej0101 rev.1.01 page 48 of 72 apr 15, 2011 5.3 peripheral function characteristics notes: 1. the a/d conversion result will be undefined in wait mode, st op mode, power-off mode, when the flash memory stops, and in low-current-consumption mode. do not perfo rm a/d conversion in these states or transition to these states during a/d conversion. 2. this applies when the peripheral functions are stopped. 3. when the analog input voltage is over the reference voltage, the a/d conversion result will be 3ffh in 10-bit mode and ffh in 8-bit mode. table 5.3 a/d converter characteristics (v cc /av cc = vref = 2.2 to 5.5 v, v ss = 0 v, and t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter conditions standard unit min. typ. max. ? resolution v ref = av cc ??10bit ? absolute accuracy (2) 10-bit mode v ref = av cc = 5.0 v an0 to an19 input ? ? 3 lsb v ref = av cc = 3.3 v an0 to an19 input ? ? 5 lsb v ref = av cc = 3.0 v an0 to an19 input ? ? 5 lsb v ref = av cc = 2.2 v an0 to an19 input ? ? 5 lsb 8-bit mode v ref = av cc = 5.0 v an0 to an19 input ? ? 2 lsb v ref = av cc = 3.3 v an0 to an19 input ? ? 2 lsb v ref = av cc = 3.0 v an0 to an19 input ? ? 2 lsb v ref = av cc = 2.2 v an0 to an19 input ? ? 2 lsb ad a/d conversion clock 4.0 v ref = av cc 5.5 v (1) 2?20mhz 3.2 v ref = av cc 5.5 v (1) 2?16mhz 2.7 v ref = av cc 5.5 v (1) 2?10mhz 2.2 v ref = av cc 5.5 v (1) 2?5mhz ? tolerance level impedance ? 3 ? k ? t conv conversion time 10-bit mode v ref = av cc = 5.0 v, ad = 20 mhz 2.2 ? ? s 8-bit mode v ref = av cc = 5.0 v, ad = 20 mhz 2.2 ? ? s t samp sampling time ad = 20 mhz 0.8 ? ? s i vref v ref current vcc = 5 v, xin = f1 = ad = 20 mhz ? 45 ? a v ref reference voltage 2.2 ? av cc v v ia analog input voltage (3) 0?v ref v ocvref on-chip reference voltage 2 mhz ad 4 mhz 1.19 1.34 1.49 v r8c/l35c group, r8c/l36c group, r8c/l38c group, r8c/l3ac group 5. electrical characteristics r01ds0095ej0101 rev.1.01 page 49 of 72 apr 15, 2011 note: 1. this applies when one d/a converter is used and the value of t he dai register (i = 0 or 1) for the unused d/a converter is 00 h. the resistor ladder of the a/d converter is not included. note: 1. when the digital filter is disabled. table 5.4 d/a converter characteristics (v cc /av cc = vref = 2.7 to 5.5 v and t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter conditions standard unit min. typ. max. ? resolution ?? 8bit ? absolute accuracy ? ? 2.5 lsb t su setup time ?? 3 s r o output resistor ? 6 ? k ? i vref reference power input current (note 1) ? ? 1.5 ma table 5.5 comparator b characteristics (v cc = 2.7 to 5.5 v and t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. vref ivref1, ivref3 input reference voltage 0 ? v cc ? 1.4 v v i ivcmp1, ivcmp3 input voltage ? 0.3 ? v cc + 0.3 v ? offset ? 5 100 mv t d comparator output delay time (1) v i = vref 100 mv ?0.1 ? s i cmp comparator operating current v cc = 5.0 v ? 17.5 ? a r8c/l35c group, r8c/l36c group, r8c/l38c group, r8c/l3ac group 5. electrical characteristics r01ds0095ej0101 rev.1.01 page 50 of 72 apr 15, 2011 notes: 1. definition of programming/erasure endurance the programming and erasure endurance is defined on a per-block basis. if the programming and erasure endurance is n (n = 1,000), each bl ock can be erased n times. for example, if 1,024 1-byte writes are performed to different addresses in block a, a 1 kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. however, the same address must not be programmed more than once per erase operati on (overwriting prohibited). 2. endurance to guarantee all electrical characteristics after program and erase. (1 to min. value can be guaranteed). 3. in a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possib le is used up before performing an erase operation. for example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. it is also advisable to retain data on the erasure endurance of each block and limit the number of erase operations to a certain number. 4. if an error occurs during block erase, attempt to execute t he clear status register command, then execute the block erase command at least three times until the erase error does not occur. 5. customers desiring program/erase failure rate information should contact their renesas te chnical support representative. 6. the data hold time includes time that the power supply is off or the clock is not supplied. table 5.6 flash memory (program rom) characteristics (v cc = 2.7 to 5.5 v and t opr = 0 to 60 c, unless otherwise specified.) symbol parameter conditions standard unit min. typ. max. ? program/erase endurance (1) 1,000 (2) ??times ? byte program time ? 80 500 s ? block erase time ? 0.3 ? s t d(sr-sus) time delay from suspend request until suspend ? ? 5 + cpu clock 3 cycles ms ? interval from erase start/restart until following suspend request 0? ? ms ? time from suspend until erase restart ? ? 30+cpu clock 1 cycle s t d(cmdrst- ready) time from when command is forcibly terminated until reading is enabled ? ? 30+cpu clock 1 cycle s ? program, erase voltage 2.7 ? 5.5 v ? read voltage 1.8 ? 5.5 v ? program, erase temperature 0 ? 60 c ? data hold time (6) ambient temperature = 55 c 20 ? ? year r8c/l35c group, r8c/l36c group, r8c/l38c group, r8c/l3ac group 5. electrical characteristics r01ds0095ej0101 rev.1.01 page 51 of 72 apr 15, 2011 notes: 1. definition of programming/erasure endurance the programming and erasure endurance is defined on a per-block basis. if the programming and erasure endurance is n (n = 10,000), each block can be erased n times. for example, if 1,024 1-byte writes are performed to different addresses in block a, a 1 kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. however, the same address must not be programmed more than once per erase operati on (overwriting prohibited). 2. endurance to guarantee all electrical characteristics after program and erase. (1 to min. value can be guaranteed). 3. in a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possib le is used up before performing an erase operation. for example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. in addition, aver aging the erasure endurance between blocks a to d can further reduce the actual erasure endurance. it is also advisable to retain data on the erasure endurance of each block and limit the number of erase operations to a certain number. 4. if an error occurs during block erase, attempt to execute t he clear status register command, then execute the block erase command at least three times until the erase error does not occur. 5. customers desiring program/erase failure rate information should contact their renesas te chnical support representative. 6. ? 40 c for d version. 7. the data hold time includes time that the po wer supply is off or the clock is not supplied. figure 5.2 time delay until suspend table 5.7 flash memory (data flash block a to block d) characteristics (v cc = 2.7 to 5.5 v and t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter conditions standard unit min. typ. max. ? program/erase endurance (1) 10,000 (2) ??times ? byte program time (program/erase endurance 1,000 times) ? 160 1500 s ? byte program time (program/erase endurance > 1,000 times) ? 300 1500 s ? block erase time (program/erase endurance 1,000 times) ?0.2 1 s ? block erase time (program/erase endurance > 1,000 times) ?0.3 1 s t d(sr-sus) time delay from suspend request until suspend ? ? 5 + cpu clock 3 cycles ms ? interval from erase start/restart until following suspend request 0? ? ms ? time from suspend until erase restart ? ? 30+cpu clock 1 cycle s t d(cmdrst- ready) time from when command is forcibly terminated until reading is enabled ? ? 30+cpu clock 1 cycle s ? program, erase voltage 2.7 ? 5.5 v ? read voltage 1.8 ? 5.5 v ? program, erase temperature ? 20 (6) ?85 c ? data hold time (7) ambient temperature = 55 c 20 ? ? year fst6 bit suspend request (fmr21 bit) fixed time clock-dependent time access restart fst6, fst7: bit in fst register fmr21: bit in fmr2 register fst7 bit t d(sr-sus) r8c/l35c group, r8c/l36c group, r8c/l38c group, r8c/l3ac group 5. electrical characteristics r01ds0095ej0101 rev.1.01 page 52 of 72 apr 15, 2011 notes: 1. select the voltage detection level with bits vdsel0 and vdsel1 in the ofs register. 2. necessary time until the voltage detection circuit operates when setting to 1 again after setting the vca25 bit in the vca2 register to 0. 3. time until the voltage monitor 0 reset is generated after the voltage passes v det0 . notes: 1. select the voltage detection level with bits vd1s0 to vd1s3 in the vd1ls register. 2. time until the voltage monitor 1 interrupt request is generated after the voltage passes v det1 . 3. necessary time until the voltage detection circuit operates when setting to 1 again after setting the vca26 bit in the vca2 register to 0. table 5.8 voltage detection 0 circuit characteristics (v cc = 1.8 to 5.5 v and t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. v det0 voltage detection level vdet0_0 (1) 1.80 1.90 2.05 v voltage detection level vdet0_1 (1) 2.15 2.35 2.50 v voltage detection level vdet0_2 (1) 2.70 2.85 3.05 v voltage detection level vdet0_3 (1) 3.55 3.80 4.05 v ? voltage detection 0 circuit response time (3) at the falling of vcc from 5 v to (vdet0_0 ? 0.1) v ? 6 150 s ? voltage detection circuit self power consumption vca25 = 1, v cc = 5.0 v ? 1.5 ? a t d(e-a) waiting time until voltage detection circuit operation starts (2) ? ? 100 s table 5.9 voltage detection 1 circuit characteristics (v cc = 1.8 to 5.5 v and t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. v det1 voltage detection level vdet1_0 (1) at the falling of v cc 2.00 2.20 2.40 v voltage detection level vdet1_1 (1) at the falling of v cc 2.15 2.35 2.55 v voltage detection level vdet1_2 (1) at the falling of v cc 2.30 2.50 2.70 v voltage detection level vdet1_3 (1) at the falling of v cc 2.45 2.65 2.85 v voltage detection level vdet1_4 (1) at the falling of v cc 2.60 2.80 3.00 v voltage detection level vdet1_5 (1) at the falling of v cc 2.75 2.95 3.15 v voltage detection level vdet1_6 (1) at the falling of v cc 2.85 3.10 3.40 v voltage detection level vdet1_7 (1) at the falling of v cc 3.00 3.25 3.55 v voltage detection level vdet1_8 (1) at the falling of v cc 3.15 3.40 3.70 v voltage detection level vdet1_9 (1) at the falling of v cc 3.30 3.55 3.85 v voltage detection level vdet1_a (1) at the falling of v cc 3.45 3.70 4.00 v voltage detection level vdet1_b (1) at the falling of v cc 3.60 3.85 4.15 v voltage detection level vdet1_c (1) at the falling of v cc 3.75 4.00 4.30 v voltage detection level vdet1_d (1) at the falling of v cc 3.90 4.15 4.45 v voltage detection level vdet1_e (1) at the falling of v cc 4.05 4.30 4.60 v voltage detection level vdet1_f (1) at the falling of v cc 4.20 4.45 4.75 v ? hysteresis width at the rising of vcc in voltage detection 1 circuit vdet1_0 to vdet1_5 selected ?0.07? v vdet1_6 to vdet1_f selected ?0.10? v ? voltage detection 1 circuit response time (2) at the falling of vcc from 5 v to (vdet1_0 ? 0.1) v ? 60 150 s ? voltage detection circuit self power consumption vca26 = 1, v cc = 5.0 v ? 1.7 ? a t d(e-a) waiting time until voltage detection circuit operation starts (3) ? ? 100 s r8c/l35c group, r8c/l36c group, r8c/l38c group, r8c/l3ac group 5. electrical characteristics r01ds0095ej0101 rev.1.01 page 53 of 72 apr 15, 2011 notes: 1. time until the voltage monitor 2 interrupt request is generated after the voltage passes v det2 . 2. necessary time until the voltage detection circuit operates afte r setting to 1 again after setting the vca27 bit in the vca2 register to 0. note: 1. to use the power-on reset function, enable voltage monitor 0 reset by setting the lvdas bit in the ofs register to 0. figure 5.3 power-on reset circuit characteristics table 5.10 voltage detection 2 circuit characteristics (v cc = 1.8 to 5.5 v and t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. v det2 voltage detection level vdet2_0 at the falling of v cc 3.70 4.00 4.30 v ? hysteresis width at the risi ng of vcc in voltage detection 2 circuit ?0.10? v ? voltage detection 2 circuit response time (1) at the falling of vcc from 5 v to (vdet2_0 ? 0.1) v ? 20 150 s ? voltage detection circuit self power consumption vca27 = 1, v cc = 5.0 v ? 1.7 ? a t d(e-a) waiting time until voltage detection circuit operation starts (2) ? ? 100 s table 5.11 power-on reset circuit characteristics (1) (t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. t rth external power v cc rise gradient 0 ? 50000 mv/msec notes: 1. v det0 indicates the voltage detection level of the voltage detection 0 circuit. refer to 6. voltage detection circuit in the user?s manual : hardware for details. 2. t w(por) indicates the duration the external power v cc must be held below the valid voltage (0.5 v) to enable a power-on reset. when turning on the power after it falls with voltage monitor 0 reset disabled, maintain t w(por) for 1 ms or more. v det0 (1) 0.5 v internal reset signal t w(por) (2) voltage detection 0 circuit response time v det0 (1) 1 f oco-s 32 1 f oco-s 32 external power v cc t rth t rth r8c/l35c group, r8c/l36c group, r8c/l38c group, r8c/l3ac group 5. electrical characteristics r01ds0095ej0101 rev.1.01 page 54 of 72 apr 15, 2011 note: 1. this enables the setting errors of bit rates such as 9600 bps and 38400 bps to be 0% when the serial interface is used in uart mode. note: 1. waiting time until the internal power s upply generation circuit stabilizes during power-on. table 5.12 high-speed on-chip osc illator circuit characteristics (v cc = 1.8 to 5.5 v and t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. ? high-speed on-chip oscillator frequency after reset v cc = 1.8 v to 5.5 v ? 20 c t opr 85 c 38.4 40 41.6 mhz v cc = 1.8 v to 5.5 v ? 40 c t opr 85 c 38.0 40 42.0 mhz high-speed on-chip oscillator frequency when the fra4 register correction value is written into the fra1 register and the fra5 register correction value into the fra3 register (1) v cc = 1.8 v to 5.5 v ? 20 c t opr 85 c 35.389 36.864 38.338 mhz v cc = 1.8 v to 5.5 v ? 40 c t opr 85 c 35.020 36.864 38.707 mhz high-speed on-chip oscillator frequency when the fra6 register correction value is written into the fra1 register and the fra7 register correction value into the fra3 register v cc = 1.8 v to 5.5 v ? 20 c t opr 85 c 30.72 32 33.28 mhz v cc = 1.8 v to 5.5 v ? 40 c t opr 85 c 30.40 32 33.60 mhz ? oscillation stability time v cc = 5.0 v, t opr = 25 c?0.53ms ? self power consumption at oscillation v cc = 5.0 v, t opr = 25 c ? 400 ? a table 5.13 low-speed on-chip osc illator circuit characteristics (v cc = 1.8 to 5.5 v and t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. foco-s low-speed on-chip oscillator frequency 112.5 125 137.5 khz ? oscillation st ability time v cc = 5.0 v, t opr = 25 c ? 30 100 s ? self power consumption at oscillation v cc = 5.0 v, t opr = 25 c? 3 ? a foco-wdt low-speed on-chip oscillator frequency for the watchdog timer 60 125 250 khz ? oscillation st ability time v cc = 5.0 v, t opr = 25 c ? 30 100 s ? self power consumption at oscillation v cc = 5.0 v, t opr = 25 c? 2 ? a table 5.14 power supply circuit characteristics (v cc = 1.8 to 5.5 v, v ss = 0 v, and t opr = 25 c, unless otherwise specified.) symbol parameter condition standard unit min. typ. max. t d(p-r) time for internal power supply stabilization during power-on (1) ? ? 2000 s r8c/l35c group, r8c/l36c group, r8c/l38c group, r8c/l3ac group 5. electrical characteristics r01ds0095ej0101 rev.1.01 page 55 of 72 apr 15, 2011 notes: 1. the voltage is selected with bits lvls0 to lvls3 in the lcr1 register. 2. refer to table 5.18 dc characteristics (2) , table 5.20 dc characteristics (4) , and table 5.22 dc characteristics (6) . 3. the vl1 voltage should be vcc or below. table 5.15 lcd drive contro l circuit char acteristics (v cc = 1.8 to 5.5 v, v ss = 0 v, and t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. vlcd lcd power supply voltage vlcd = vl4 2.2 ? 5.5 v vl3 vl3 voltage vl2 ? vl4 v vl2 vl2 voltage r8c/l35c vl1 ? vl4 v r8c/l36c, r8c/l38c, r8c/l3ac vl1 ? vl3 v vl1 vl1 voltage 1? vl2 (3) v ? vl1 internally-generated voltage accuracy (1) setting voltage ? 0.2 setting voltage setting voltage +0.2 v f(fr) frame frequency 50 ? 180 hz ilcd lcd drive control circuit current ? (note 2) ? a table 5.16 power-off mode characteristics (v cc = 2.2 to 5.5 v, v ss = 0 v, and t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. ? power-off mode operating supply voltage 2.2 ? 5.5 v r8c/l35c group, r8c/l36c group, r8c/l38c group, r8c/l3ac group 5. electrical characteristics r01ds0095ej0101 rev.1.01 page 56 of 72 apr 15, 2011 5.4 dc characteristics note: 1. this applies when the drive capacity of the output transistor is set to high by registers p10drr and p11drr. when the drive capacity is set to low, the value of any other pin applies. table 5.17 dc characteristics (1) [4.0 v vcc 5.5 v] (t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. v oh output ?h? voltage port p10, p11 (1) v cc = 5v i oh = ? 20 ma v cc ? 2.0 ? v cc v other pins v cc = 5v i oh = ? 5 ma v cc ? 2.0 ? v cc v xout v cc = 5v i oh = ? 200 a1.0??v v ol output ?l? voltage port p10, p11 (1) v cc = 5v i ol = 20 ma ??2.0v other pins v cc = 5v i ol = 5 ma ? ? 2.0 v xout v cc = 5v i ol = 200 a??0.5v v t+- v t- hysteresis int0 , int1 , int2 , int3 , int4 , int5 , int6 , int7 , ki0 , ki1 , ki2 , ki3 , ki4 , ki5 , ki6 , ki7 , traio, trcioa, trciob, trcioc, trciod, trdioa0, trdiob0, trdioc0, trdiod0, trdioa1, trdiob1, trdioc1, trdiod1, trctrg, trcclk, trgclka, trgclkb, trgioa, trgiob, adtrg , rxd0, rxd1, rxd2, clk0, clk1, clk2, ssi, scl, sda, sso 0.05 0.5 ? v reset , wkup0 0.1 1.0 ? v i ih input ?h? current vi = 5.0 v, v cc = 5.0 v ? ? 5.0 a i il input ?l? current vi = 0 v, v cc = 5.0 v ? ? ? 5.0 a r pullup pull-up resistance vi = 0 v, v cc = 5.0 v 25 50 100 k ? r fxin feedback resistance xin ? 0.3 ? m ? r fxcin feedback resistance xcin ? 14 ? m ? v ram ram hold voltage during stop mode 1.8 ? ? v r8c/l35c group, r8c/l36c group, r8c/l38c group, r8c/l3ac group 5. electrical characteristics r01ds0095ej0101 rev.1.01 page 57 of 72 apr 15, 2011 notes: 1. vcc = 4.0 v to 5.5 v, single chip mode, output pins are open, and other pins are vss. 2. xin is set to square wave input. 3. vcc = 5.0 v 4. vlcd = vcc, external division resistors are used for vl4 to vl1, 1/3 bias, 1/4 duty, f(fr) = 64 hz, seg0 to seg55 are selecte d, and segment and common output pins are open. the standard value does not include the current that flows through external division resistors . 5. the internal voltage multiplier is used, bits lvls3 to lvls0 in the lcr1 register = 1011b, 1/3 bias, 1/4 duty, f(fr) = 64 hz, seg0 to seg55 are selected, and segment and common output pins are open. table 5.18 dc characteristics (2) [4.0 v vcc 5.5 v] (t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit oscillation circuit on-chip oscillator cpu clock low-power- consumption setting other min. typ. (3) max. xin (2) xcin high-speed (foco-f) low- speed i cc power supply current (1) high- speed clock mode 20 mhz off off 125 khz no division ??7.015ma 16 mhz off off 125 khz no division ? ? 5.6 12.5 ma 10 mhz off off 125 khz no division ??3.6?ma 20 mhz off off 125 khz divide- by-8 ??3.0?ma 16 mhz off off 125 khz divide- by-8 ??2.2?ma 10 mhz off off 125 khz divide- by-8 ??1.5?ma high- speed on-chip oscillator mode off off 20 mhz 125 khz no division ??7.015ma off off 20 mhz 125 khz divide- by-8 ??3.0?ma off off 4 mhz 125 khz divide- by-16 mstiic = 1 msttrd = 1 msttrc = 1 msttrg = 1 ?1?ma low- speed on-chip oscillator mode off off off 125 khz divide- by-8 fmr27 = 1 vca20 = 0 ? 90 400 a low- speed clock mode off 32 khz off off no division fmr27 = 1 vca20 = 0 ? 100 400 a off 32 khz off off no division fmstp = 1 vca20 = 0 flash memory off program operation on ram ?55? a wait mode off off off 125 khz ? vca27 = 0 vca26 = 0 vca25 = 0 vca20 = 1 while a wait instruction is executed peripheral clock operation ? 15 100 a off off off 125 khz ? vca27 = 0 vca26 = 0 vca25 = 0 vca20 = 1 cm02 = 1 cm01 = 1 while a wait instruction is executed peripheral clock off ?490 a off 32 khz off off ? vca27 = 0 vca26 = 0 vca25 = 0 vca20 = 1 cm02 = 1 cm01 = 0 while a wait instruction is executed peripheral clock off timer re operation in real-time clock mode lcd drive control circuit (4) when external division resistors are used ?7? a lcd drive control circuit (5) when the internal voltage multiplier is used ?12? a off 32 khz off off ? vca27 = 0 vca26 = 0 vca25 = 0 vca20 = 1 cm02 = 1 cm01 = 1 while a wait instruction is executed peripheral clock off timer re operation in real-time clock mode ?3.5? a stop mode off off off off ? vca27 = 0 vca26 = 0 vca25 = 0 cm10 = 1 topr = 25 c peripheral clock off ?2.05.0 a off off off off ? vca27 = 0 vca26 = 0 vca25 = 0 cm10 = 1 topr = 85 c peripheral clock off ?15? a power- off mode off off off off ? ? topr = 25 c ? 0.02 0.2 a off off off off ? ? topr = 85 c?0.4? a r8c/l35c group, r8c/l36c group, r8c/l38c group, r8c/l3ac group 5. electrical characteristics r01ds0095ej0101 rev.1.01 page 58 of 72 apr 15, 2011 note: 1. this applies when the drive capacity of the output transistor is set to high by registers p10drr and p11drr. when the drive capacity is set to low, the value of any other pin applies. table 5.19 dc characteristics (3) [2.7 v vcc < 4.0 v] (t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. v oh output ?h? voltage port p10, p11 (1) i oh = ? 5 ma v cc ? 0.5 ? v cc v other pins i oh = ? 1 ma v cc ? 0.5 ? v cc v xout i oh = ? 200 a1.0??v v ol output ?l? voltage port p10, p11 (1) i ol = 5 ma ??0.5v other pins i ol = 1 ma ? ? 0.5 v xout i ol = 200 a??0.5v v t+- v t- hysteresis int0 , int1 , int2 , int3 , int4 , int5 , int6 , int7 , ki0 , ki1 , ki2 , ki3 , ki4 , ki5 , ki6 , ki7 , traio, trcioa, trciob, trcioc, trciod, trdioa0, trdiob0, trdioc0, trdiod0, trdioa1, trdiob1, trdioc1, trdiod1, trctrg, trcclk, trgclka, trgclkb, trgioa, trgiob, adtrg , rxd0, rxd1, rxd2, clk0, clk1, clk2, ssi, scl, sda, sso 0.05 0.4 ? v reset , wkup0 0.1 0.8 ? v i ih input ?h? current vi = 3.0 v, v cc = 3.0 v ? ? 5.0 a i il input ?l? current vi = 0 v, v cc = 3.0 v ? ? ? 5.0 a r pullup pull-up resistance vi = 0 v, v cc = 3.0 v 30 100 170 k ? r fxin feedback resistance xin ? 0.3 ? m ? r fxcin feedback resistance xcin ? 14 ? m ? v ram ram hold voltage during stop mode 1.8 ? ? v r8c/l35c group, r8c/l36c group, r8c/l38c group, r8c/l3ac group 5. electrical characteristics r01ds0095ej0101 rev.1.01 page 59 of 72 apr 15, 2011 notes: 1. vcc = 2.7 v to 4.0 v, single chip mode, output pins are open, and other pins are vss. 2. xin is set to square wave input. 3. vcc = 3.0 v 4. vlcd = vcc, external division resistors are used for vl4 to vl1, 1/3 bias, 1/4 duty, f(fr) = 64 hz, seg0 to seg55 are selecte d, and segment and common output pins are open. the standard value does not include the current that flows through external division resistors . 5. the internal voltage multiplier is used, bits lvls3 to lvls0 in the lcr1 register = 1011b, 1/3 bias, 1/4 duty, f(fr) = 64 hz, seg0 to seg55 are selected, and segment and common output pins are open. table 5.20 dc characteristics (4) [2.7 v vcc < 4.0 v] (t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit oscillation circuit on-chip oscillator cpu clock low-power- consumption setting other min. typ. (3) max. xin (2) xcin high-speed (foco-f) low- speed i cc power supply current (1) high- speed clock mode 20 mhz off off 125 khz no division ??7.014.5ma 10 mhz off off 125 khz no division ??3.610ma 20 mhz off off 125 khz divide- by-8 ??3.0?ma 10 mhz off off 125 khz divide- by-8 ??1.5?ma high- speed on-chip oscillator mode off off 20 mhz 125 khz no division ??7.014.5ma off off 20 mhz 125 khz divide- by-8 ??3.0?ma off off 10 mhz 125 khz no division ??4.0?ma off off 10 mhz 125 khz divide- by-8 ??1.7?ma off off 4 mhz 125 khz divide- by-16 mstiic = 1 msttrd = 1 msttrc = 1 msttrg = 1 ?1?ma low- speed on-chip oscillator mode off off off 125 khz divide- by-8 fmr27 = 1 vca20 = 0 ?85390 a low- speed clock mode off 32 khz off off no division fmr27 = 1 vca20 = 0 ?90400 a off 32 khz off off no division fmstp = 1 vca20 = 0 flash memory off program operation on ram ?50? a wait mode off off off 125 khz ? vca27 = 0 vca26 = 0 vca25 = 0 vca20 = 1 while a wait instruction is executed peripheral clock operation ?1590 a off off off 125 khz ? vca27 = 0 vca26 = 0 vca25 = 0 vca20 = 1 cm02 = 1 cm01 = 1 while a wait instruction is executed peripheral clock off ?580 a off 32 khz off off ? vca27 = 0 vca26 = 0 vca25 = 0 vca20 = 1 cm02 = 1 cm01 = 0 while a wait instruction is executed peripheral clock off timer re operation in real-time clock mode lcd drive control circuit (4) when external division resistors are used ?5? a lcd drive control circuit (5) when the internal voltage multiplier is used ?11? a off 32 khz off off ? vca27 = 0 vca26 = 0 vca25 = 0 vca20 = 1 cm02 = 1 cm01 = 1 while a wait instruction is executed peripheral clock off timer re operation in real-time clock mode ?3.5? a stop mode off off off off ? vca27 = 0 vca26 = 0 vca25 = 0 cm10 = 1 topr = 25 c peripheral clock off ?25.0 a off off off off ? vca27 = 0 vca26 = 0 vca25 = 0 cm10 = 1 topr = 85 c peripheral clock off ? 13.0 ? a power- off mode off off off off ? ? topr = 25 c ? 0.02 0.2 a off off off off ? ? topr = 85 c?0.3? a r8c/l35c group, r8c/l36c group, r8c/l38c group, r8c/l3ac group 5. electrical characteristics r01ds0095ej0101 rev.1.01 page 60 of 72 apr 15, 2011 note: 1. this applies when the drive capacity of the output transistor is set to high by registers p10drr and p11drr. when the drive capacity is set to low, the value of any other pin applies. table 5.21 dc characteristics (5) [1.8 v vcc < 2.7 v] (t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. v oh output ?h? voltage port p10, p11 (1) i oh = ? 2 ma v cc ? 0.5 ? v cc v other pins i oh = ? 1 ma v cc ? 0.5 ? v cc v xout i oh = ? 200 a1.0??v v ol output ?l? voltage port p10, p11 (1) i ol = 2 ma ??0.5v other pins i ol = 1 ma ? ? 0.5 v xout i ol = 200 a??0.5v v t+- v t- hysteresis int0 , int1 , int2 , int3 , int4 , int5 , int6 , int7 , ki0 , ki1 , ki2 , ki3 , ki4 , ki5 , ki6 , ki7 , traio, trcioa, trciob, trcioc, trciod, trdioa0, trdiob0, trdioc0, trdiod0, trdioa1, trdiob1, trdioc1, trdiod1, trctrg, trcclk, trgclka, trgclkb, trgioa, trgiob, adtrg , rxd0, rxd1, rxd2, clk0, clk1, clk2, ssi, scl, sda, sso 0.05 0.4 ? v reset , wkup0 0.1 0.8 ? v i ih input ?h? current vi = 1.8 v, v cc = 1.8 v ? ? 4.0 a i il input ?l? current vi = 0 v, v cc = 1.8 v ? ? ? 4.0 a r pullup pull-up resistance vi = 0 v, v cc = 1.8 v 60 160 420 k ? r fxin feedback resistance xin ? 0.3 ? m ? r fxcin feedback resistance xcin ? 14 ? m ? v ram ram hold voltage during stop mode 1.8 ? ? v r8c/l35c group, r8c/l36c group, r8c/l38c group, r8c/l3ac group 5. electrical characteristics r01ds0095ej0101 rev.1.01 page 61 of 72 apr 15, 2011 notes: 1. vcc = 1.8 v to 2.7 v, single chip mode, output pins are open, and other pins are vss. 2. xin is set to square wave input. 3. vcc = 2.2 v 4. vlcd = vcc, external division resistors are used for vl4 to vl1, 1/3 bias, 1/4 duty, f(fr) = 64 hz, seg0 to seg55 are selecte d, and segment and common output pins are open.the standard value does not includ e the current that flows through external division resistors. 5. the internal voltage multiplier is used, bits lvls3 to lvls0 in the lcr1 register = 1011b, 1/3 bias, 1/4 duty, f(fr) = 64 hz, seg0 to seg55 are selected, and segment and common output pins are open. table 5.22 dc characteristics (6) [1.8 v vcc < 2.7 v] (t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit oscillation circuit on-chip oscillator cpu clock low-power- consumption setting other min. typ. (3) max. xin (2) xcin high-speed (foco-f) low- speed i cc power supply current (1) high- speed clock mode 5 mhz off off 125 khz no division ??2.2?ma 5 mhz off off 125 khz divide- by-8 ??0.8?ma high- speed on-chip oscillator mode off off 5 mhz 125 khz no division ??2.510ma off off 5 mhz 125 khz divide- by-8 ??1.7?ma off off 4 mhz 125 khz divide- by-16 mstiic = 1 msttrd = 1 msttrc = 1 msttrg = 1 ?1?ma low- speed on-chip oscillator mode off off off 125 khz divide- by-8 fmr27 = 1 vca20 = 0 ?90300 a low- speed clock mode off 32 khz off off no division fmr27 = 1 vca20 = 0 ?90400 a off 32 khz off off no division fmstp = 1 vca20 = 0 flash memory off program operation on ram ?45? a wait mode off off off 125 khz ? vca27 = 0 vca26 = 0 vca25 = 0 vca20 = 1 while a wait instruction is executed peripheral clock operation ?1590 a off off off 125 khz ? vca27 = 0 vca26 = 0 vca25 = 0 vca20 = 1 cm02 = 1 cm01 = 1 while a wait instruction is executed peripheral clock off ?480 a off 32 khz off off ? vca27 = 0 vca26 = 0 vca25 = 0 vca20 = 1 cm02 = 1 cm01 = 0 while a wait instruction is executed peripheral clock off timer re operation in real-time clock mode lcd drive control circuit (4) when external division resistors are used ?4? a lcd drive control circuit (5) when the internal voltage multiplier is used ?11? a off 32 khz off off ? vca27 = 0 vca26 = 0 vca25 = 0 vca20 = 1 cm02 = 1 cm01 = 1 while a wait instruction is executed peripheral clock off timer re operation in real-time clock mode ?3.5? a stop mode off off off off ? vca27 = 0 vca26 = 0 vca25 = 0 cm10 = 1 topr = 25 c peripheral clock off ?2.05.0 a off off off off ? vca27 = 0 vca26 = 0 vca25 = 0 cm10 = 1 topr = 85 c peripheral clock off ?13? a power- off mode off off off off ? ? topr = 25 c ? 0.02 0.2 a off off off off ? ? topr = 85 c?0.3? a r8c/l35c group, r8c/l36c group, r8c/l38c group, r8c/l3ac group 5. electrical characteristics r01ds0095ej0101 rev.1.01 page 62 of 72 apr 15, 2011 5.5 ac characteristics note: 1. 1t cyc = 1/f1(s) table 5.23 timing requirements of synchronous serial communication unit (ssu) (v cc = 1.8 to 5.5 v, v ss = 0 v, and t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter conditions standard unit min. typ. max. t sucyc ssck clock cycle time 4? ? t cyc (1) t hi ssck clock ?h? width 0.4 ? 0.6 t sucyc t lo ssck clock ?l? width 0.4 ? 0.6 t sucyc t rise ssck clock rising time master ?? 1 t cyc (1) slave ? ? 1 s t fall ssck clock falling time master ?? 1 t cyc (1) slave ? ? 1 s t su sso, ssi data input setup time 100 ? ? ns t h sso, ssi data input hold time 1? ? t cyc (1) t lead scs setup time slave 1t cyc + 50 ? ? ns t lag scs hold time slave 1t cyc + 50 ? ? ns t od sso, ssi data output delay time ?? 1 t cyc (1) t sa ssi slave access time 2.7 v v cc 5.5 v ? ? 1.5t cyc + 100 ns 1.8 v v cc < 2.7 v ? ? 1.5t cyc + 200 ns t or ssi slave out open time 2.7 v v cc 5.5 v ? ? 1.5t cyc + 100 ns 1.8 v v cc < 2.7 v ? ? 1.5t cyc + 200 ns r8c/l35c group, r8c/l36c group, r8c/l38c group, r8c/l3ac group 5. electrical characteristics r01ds0095ej0101 rev.1.01 page 63 of 72 apr 15, 2011 figure 5.4 i/o timing of synchronous serial communication unit (ssu) (master) v ih or v oh v il or v ol t hi t lo t hi t fall t rise t lo t sucyc t od t h t su scs (output) ssck (output) (cpos = 1) ssck (output) (cpos = 0) sso (output) ssi (input) 4-wire bus communication mode, master, cphs = 1 v ih or v oh v il or v ol t hi t lo t hi t fall t rise t lo t sucyc t od t h t su scs (output) ssck (output) (cpos = 1) ssck (output) (cpos = 0) sso (output) ssi (input) 4-wire bus communication mode, master, cphs = 0 cphs, cpos: bits in ssmr register r8c/l35c group, r8c/l36c group, r8c/l38c group, r8c/l3ac group 5. electrical characteristics r01ds0095ej0101 rev.1.01 page 64 of 72 apr 15, 2011 figure 5.5 i/o timing of synchronous serial communication unit (ssu) (slave) v ih or v oh v il or v ol scs (input) ssck (input) (cpos = 1) ssck (input) (cpos = 0) sso (input) ssi (output) 4-wire bus communication mode, slave, cphs = 1 v ih or v oh v il or v ol t hi t lo t hi t fall t rise t lo t sucyc t h t su scs (input) ssck (input) (cpos = 1) ssck (input) (cpos = 0) sso (input) ssi (output) 4-wire bus communication mode, slave, cphs = 0 t od t lead t sa t lag t or t hi t lo t hi t fall t rise t lo t sucyc t h t su t od t lead t sa t lag t or cphs, cpos: bits in ssmr register r8c/l35c group, r8c/l36c group, r8c/l38c group, r8c/l3ac group 5. electrical characteristics r01ds0095ej0101 rev.1.01 page 65 of 72 apr 15, 2011 figure 5.6 i/o timing of synchronous serial communication unit (ssu) (clock synchronous communication mode) v ih or v oh t hi t lo t sucyc t od t h t su ssck sso (output) ssi (input) v il or v ol r8c/l35c group, r8c/l36c group, r8c/l38c group, r8c/l3ac group 5. electrical characteristics r01ds0095ej0101 rev.1.01 page 66 of 72 apr 15, 2011 note: 1. 1t cyc = 1/f1(s) figure 5.7 i/o timing of i 2 c bus interface table 5.24 timing requirements of i 2 c bus interface (1) (v cc = 1.8 to 5.5 v, v ss = 0 v, and t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. t scl scl input cycle time 12t cyc + 600 (1) ??ns t sclh scl input ?h? width 3t cyc + 300 (1) ??ns t scll scl input ?l? width 5t cyc + 500 (1) ??ns t sf scl, sda input fall time ? ? 300 ns t sp scl, sda input spike pulse rejection time ?? 1t cyc (1) ns t buf sda input bus-free time 5t cyc (1) ??ns t stah start condition input hold time 3t cyc (1) ??ns t stas retransmit start condition input setup time 3t cyc (1) ??ns t stop stop condition input setup time 3t cyc (1) ??ns t sdas data input setup time 1t cyc + 40 (1) ??ns t sdah data input hold time 10 ? ? ns sda t stah t scll t buf v ih v il t sclh scl t sr t sf t sdah t scl t stas t sp t stop t sdas p (2) s (1) sr (3) p (2) notes: 1. start condition 2. stop condition 3. retransmit start condition r8c/l35c group, r8c/l36c group, r8c/l38c group, r8c/l3ac group 5. electrical characteristics r01ds0095ej0101 rev.1.01 page 67 of 72 apr 15, 2011 figure 5.8 external clock input timing diagram figure 5.9 input timing of traio table 5.25 external clock input (xin, xcin) (v cc = 1.8 to 5.5 v, v ss = 0 v, and t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter standard unit v cc = 2.2v, topr = 25 c v cc = 3v, topr = 25 cv cc = 5v, topr = 25 c min. max. min. max. min. max. t c(xin) xin input cycle time 200 ? 50 ? 50 ? ns t wh(xin) xin input ?h? width 90 ? 24 ? 24 ? ns t wl(xin) xin input ?l? width 90 ? 24 ? 24 ? ns t c(xcin) xcin input cycle time 14 ? 14 ? 14 ? s t wh(xcin) xcin input ?h? width 7 ? 7 ? 7 ? s t wl(xcin) xcin input ?l? width 7 ? 7 ? 7 ? s table 5.26 timing requirements of traio (v cc = 1.8 to 5.5 v, v ss = 0 v and t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter standard unit v cc = 2.2v, topr = 25 c v cc = 3v, topr = 25 cv cc = 5v, topr = 25 c min. max. min. max. min. max. t c(traio) traio input cycle time 500 ? 300 ? 100 ? ns t wh(traio) traio input ?h? width 200 ? 120 ? 40 ? ns t wl(traio) traio input ?l? width 200 ? 120 ? 40 ? ns external clock input t wh(xin), t wh(xcin) t c(xin), t c(xcin) t wl(xin), t wl(xcin) traio input t c(traio) t wl(traio) t wh(traio) r8c/l35c group, r8c/l36c group, r8c/l38c group, r8c/l3ac group 5. electrical characteristics r01ds0095ej0101 rev.1.01 page 68 of 72 apr 15, 2011 i = 0 to 2 figure 5.10 input and output timing of serial interface notes: 1. when selecting the digital filter by the inti input filter select bit, use an inti input high width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. 2. when selecting the digital filter by the inti input filter select bit, use an inti input low width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. figure 5.11 input timing of external interrupt int i and key input interrupt kii table 5.27 timing requirements of serial interface (v cc = 1.8 to 5.5 v, v ss = 0 v, and t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter standard unit v cc = 2.2v, topr = 25 cv cc = 3v, topr = 25 cv cc = 5v, topr = 25 c min. max. min. max. min. max. t c(ck) clki input cycle time 800 ? 300 ? 200 ? ns t w(ckh) clki input ?h? width 400 ? 150 ? 100 ? ns t w(ckl) clki input ?l? width 400 ? 150 ? 100 ? ns t d(c-q) txdi output delay time ? 200 ? 80 ? 50 ns t h(c-q) txdi hold time 0 ? 0 ? 0 ? ns t su(d-c) rxdi input setup time 150 ? 70 ? 50 ? ns t h(c-d) rxdi input hold time 90 ? 90 ? 90 ? ns table 5.28 timing requirements of external interrupt inti (i = 0 to 7) and key input interrupt kii (i = 0 to 7) (v cc = 1.8 to 5.5 v, v ss = 0 v, and t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter standard unit v cc = 2.2v, topr = 25 cv cc = 3v, topr = 25 cv cc = 5v, topr = 25 c min. max. min. max. min. max. t w(inh) inti input ?h? width, kii input ?h? width 1000 (1) ? 380 (1) ? 250 (1) ? ns t w(inl) inti input ?l? width, kii input ?l? width 1000 (2) ? 380 (2) ? 250 (2) ? ns t w(ckh) t c(ck) t w(ckl) t h(c-q) t h(c-d) t su(d-c) t d(c-q) clki txdi rxdi i = 0 to 2 inti input (i = 0 to 7) t w(inl) t w(inh) kii input (i = 0 to 7) r8c/l35c group, r8c/l36c group, r8c/l38c gr oup, r8c/l3ac group package dimensions r01ds0095ej0101 rev.1.01 page 69 of 72 apr 15, 2011 package dimensions diagrams showing the latest package di mensions and mounting information are available in the ?p ackages? section of the renesas electronics web site. include trim offset. dimension "*3" does not note) do not include mold flash. dimensions "*1" and "*2" 1. 2. detail f c a l1 l a2 a1 index mark x * 3 * 1 * 2 f 39 27 13 1 40 52 26 14 zd ze d hd e he bp terminal cross section c bp c1 b1 previous code jeita package code renesas code plqp0052ja-a 52p6a-a mass[typ.] 0.3g p-lqfp52-10x10-0.65 1.0 0.125 0.30 1.1 1.1 0.13 0.20 0.145 0.09 0.37 0.32 0.27 max nom min dimension in millimeters symbol reference 10.1 10.0 9.9 d 10.1 10.0 9.9 e 1.4 a 2 12.2 12.0 11.8 12.2 12.0 11.8 1.7 a 0.15 0.1 0.05 0.65 0.5 0.35 l x 8 0 c 0.65 e 0.10 y h d h e a 1 b p b 1 c 1 z d z e l 1 e y s s r8c/l35c group, r8c/l36c group, r8c/l38c gr oup, r8c/l3ac group package dimensions r01ds0095ej0101 rev.1.01 page 70 of 72 apr 15, 2011 terminal cross section b 1 c 1 b p c 2. 1. dimensions " * 1" and " * 2" do not include mold flash. note) dimension " * 3" does not include trim offset. index mark * 3 17 32 64 49 116 33 48 f * 1 * 2 x b p h e e h d d z d z e detail f a c a 2 a 1 l 1 l p-lqfp64-10x10-0.50 0.3g mass[typ.] 64p6q-a / fp-64k / fp-64kv plqp0064kb-a renesas code jeita package code previous code 1.0 0.125 0.18 1.25 1.25 0.08 0.20 0.145 0.09 0.25 0.20 0.15 max nom min dimension in millimeters symbol reference 10.1 10.0 9.9 d 10.1 10.0 9.9 e 1.4 a 2 12.2 12.0 11.8 12.2 12.0 11.8 1.7 a 0.15 0.1 0.05 0.65 0.5 0.35 l x 8 0 c 0.5 e 0.08 y h d h e a 1 b p b 1 c 1 z d z e l 1 e y s s terminal cross section b1 c1 bp c 2. 1. dimensions " * 1" and " * 2" do not include mold flash. note) dimension " * 3" does not include trim offset. * 3 116 17 32 33 48 49 64 f * 1 * 2 x index mark d h d e h e e b p z d z e detail f c a a 2 a 1 l l 1 previous code jeita package code renesas code plqp0064ga-a 64p6u-a/ ? mass[typ.] 0.7g p-lqfp64-14x14-0.80 1.0 0.125 0.35 1.0 1.0 0.20 0.20 0.145 0.09 0.42 0.37 0.32 max nom min dimension in millimeters symbol reference 14.1 14.0 13.9 d 14.1 14.0 13.9 e 1.4 a 2 16.2 16.0 15.8 16.2 16.0 15.8 1.7 a 0.2 0.1 0 0.7 0.5 0.3 l x 8 0 c 0.8 e 0.10 y h d h e a 1 b p b 1 c 1 z d z e l 1 y s s r8c/l35c group, r8c/l36c group, r8c/l38c gr oup, r8c/l3ac group package dimensions r01ds0095ej0101 rev.1.01 page 71 of 72 apr 15, 2011 detail f c a l 1 l a 1 a 2 index mark * 2 * 1 * 3 f 80 61 60 41 40 21 20 1 x z e z d e h e d h d e b p 2. 1. dimensions " * 1" and " * 2" do not include mold flash. note) dimension " * 3" does not include trim offset. previous code jeita package code renesas code plqp0080kb-a 80p6q-a mass[typ.] 0.5g p-lqfp80-12x12-0.50 1.0 0.125 0.18 1.25 1.25 0.08 0.20 0.145 0.09 0.25 0.20 0.15 max nom min dimension in millimeters symbol reference 12.1 12.0 11.9 d 12.1 12.0 11.9 e 1.4 a 2 14.2 14.0 13.8 14.2 14.0 13.8 1.7 a 0.2 0.1 0 0.7 0.5 0.3 l x 10 0 c 0.5 e 0.08 y h d h e a 1 b p b 1 c 1 z d z e l 1 terminal cross section c bp c 1 b 1 y s s l 1 z e z d c 1 b 1 b p a 1 h e h d y 0.10 e 0.65 c 0 8 x l 0.35 0.5 0.65 0.05 0.1 0.15 a 1.7 15.8 16.0 16.2 15.8 16.0 16.2 a 2 1.4 e 13.9 14.0 14.1 d 13.9 14.0 14.1 reference symbol dimension in millimeters min nom max 0.27 0.32 0.37 0.09 0.145 0.20 0.13 0.825 0.825 0.30 0.125 1.0 p-lqfp80-14x14-0.65 0.6g mass[typ.] fp-80w / fp-80wv plqp0080ja-a renesas code jeita package code previous code include trim offset. dimension " * 3" does not note) do not include mold flash. dimensions " * 1" and " * 2" 1. 2. c 1 c b p b 1 terminal cross section a 2 c l a 1 a l 1 detail f z e z d h e h d d e * 2 * 1 * 3 f 80 61 60 41 40 21 20 1 index mark e b p m s ys r8c/l35c group, r8c/l36c group, r8c/l38c gr oup, r8c/l3ac group package dimensions r01ds0095ej0101 rev.1.01 page 72 of 72 apr 15, 2011 terminal cross section b 1 c 1 b p c 2. 1. dimensions " * 1" and " * 2" do not include mold flash. note) dimension " * 3" does not include trim offset. index mark x 125 26 50 51 75 76 100 f * 1 *3 * 2 z e z d e d h d h e b p detail f l 1 a 2 a 1 l a c l 1 z e z d c 1 b 1 b p a 1 h e h d y 0.08 e 0.5 c 0 8 x l 0.35 0.5 0.65 0.05 0.1 0.15 a 1.7 15.8 16.0 16.2 15.8 16.0 16.2 a 2 1.4 e 13.9 14.0 14.1 d 13.9 14.0 14.1 reference symbol dimension in millimeters min nom max 0.15 0.20 0.25 0.09 0.145 0.20 0.08 1.0 1.0 0.18 0.125 1.0 previous code jeita package code renesas code plqp0100kb-a 100p6q-a / fp-100u / fp-100uv mass[typ.] 0.6g p-lqfp100-14x14-0.50 e y s s p-qfp100-14x20-0.65 1.8g mass[typ.] 100p6f-a prqp0100jd-b renesas code jeita package code previous code 0.2 0.15 0.13 0.4 0.3 0.25 max nom min dimension in millimeters symbol reference 20.2 20.0 19.8 d 14.2 14.0 13.8 e 2.8 a 2 23.1 22.8 22.5 17.1 16.8 16.5 3.05 a 0.2 0.1 0 0.8 0.6 0.4 l 10 0 c 0.65 e 0.10 y h d h e a 1 b p z d z e 0.575 0.825 x 0.13 2. 1. dimensions " * 1" and " * 2" do not include mold flash. note) dimension " * 3" does not include trim offset. detail f l a 2 a 1 * 3 * 1 * 2 f 1 30 31 50 51 80 81 100 index mark x c h e e d h d a b p z d z e e y s s c - 1 r8c/l35c group, r8c/l36c group, r8c/l38c group, r8c/l3ac group datasheet rev. date description page summary 0.10 oct 30, 2009 ? first edition issued 0.20 apr 15, 2011 6 table 1.6 function de leted, current consumption revised 7 1.2 ?of r8c/lx series? ?for each group? 7 to 10 tables 1.7 to 1.10 revised 24 table 1.15 ?voltage detection circuit? deleted 29 4. special function registers (sfrs) ?the description offered in this chapter is based on the r8c/l3ac group.? added 45 to 68 5. electrical characteristics added 1.00 jun 25, 2010 ? ?preliminary? and ?under development? deleted 1 1.1 revised 7 to 10 tables 1.7 to 1.10 revised 45 tables 5.1 note 2 added 55 table 5.15 note 3 added 69 to 72 package dimensions revised 1.01 apr 15, 2011 2 table 1.1 revised 3 table 1.2 note 2, table 1.3 note 1 revised 6 table 1.6 ?flash memory? revised 11 to 14 figure 1.5 to figure 1.8 revised 20 to 22 table 1.11 to table 1.13 ?voltage detection circuit? deleted 23, 24 table 1.14 and table 1.15 title ?for r8c/l3ac group? added 28 3. ?the internal rom ... with address 0ffffh.? deleted 38 to 40 table 4.10 to table 4.12 ?0248h to 026fh?, ?02a8h to 02bfh?, ?02c0h to 02cfh? revised 48 table 5.3 ?t conv ?, ?t samp ? revised 57, 59, 61 table 5.18, table 5.20, table 5.22 ?high-speed? ?high-speed (foco-f)? all trademarks and registered trademarks are the property of their respective owners. revision history general precautions in the handling of mpu/mcu products the following usage notes are applicable to all mpu/mcu products from renesas. for detailed usage notes on the products covered by this manual, refer to the rele vant sections of the manu al. if the descriptions under general precautions in the handling of mpu/mcu products and in the body of the manual differ from each other, the description in the bod y of the manual takes precedence. 1. handling of unused pins handle unused pins in accord with the directi ons given under handling of unused pins in the manual. ? the input pins of cmos products are general ly in the high-impedance state. in operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of lsi, an associated shoot-through cu rrent flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. unused pins should be handled as described under handling of unused pins in the manual. 2. processing at power-on the state of the product is undefined at the moment when power is supplied. ? the states of internal circuits in the lsi are indeterminate and the states of register settings and pins are undefined at t he moment when power is supplied. in a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. in a similar way, the states of pins in a pr oduct that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. prohibition of access to reserved addresses access to reserved addresses is prohibited. ? the reserved addresses are provided for the po ssible future expansion of functions. do not access these addresses; the correct operat ion of lsi is not guaranteed if they are accessed. 4. clock signals after applying a reset, only release the reset line after the operating clock signal has become stable. when switching the clock signal during pr ogram execution, wait until the target clock signal has stabilized. ? when the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset li ne is only released after full stabilization of the clock signal. moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. differences between products before changing from one product to another, i.e. to one with a different part number, confirm that the change will not lead to problems. ? the characteristics of mpu/mcu in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern. when changing to products of different part numbe rs, implement a system-evaluation test for each of the products. notice 1. all information included in this document is current as of the date this document is issued. such information, however, is s ubject to change without any prior notice. before purchasing or using any renesas electronics products listed herein, please confirm the latest product information with a renesas electronics sales office. also , please pay regular and careful attention to additional and different information to be disclosed by renesas electronics such as that disclosed through our website. 2. renesas electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electronics products or technical information described in this document. no license, express, implied or otherwise, is granted hereby under any paten ts, copyrights or other intellectual property rights of renesas electronics or others. 3. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part . 4. descriptions of circuits, software and other related information in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. when exporting the products or technology described in this document, you should comply with the applicable export control l aws and regulations and follow the procedures required by such laws and regulations. you should not use renesas electronics products or the technology described in this document for any purpose rela ting to military applications or use by the military, including but not limited to the development of weapons of mass destruction. renesas electronics products and technology may not be used for or incorporate d into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 6. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information incl uded herein. 7. renesas electronics products are classified according to the following three quality grades: "standard", "high quality", an d "specific". the recommended applications for each renesas electronics product depends on the product's quality grade, as indicated below. you must check the quality grade of each renesas electronics produ ct before using it in a particular application. you may not use any renesas electronics product for any application categorized as "specific" without the prior written consent of renesas electronics. fu rther, you may not use any renesas electronics product for any application for which it is not intended without the prior written consent of renesas electronics. renesas electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any renesas electronics product for an application categorized as "specific" or for which the product is not intended wh ere you have failed to obtain the prior written consent of renesas electronics. the quality grade of each renesas electronics product is "standard" unless otherwise expressly specified in a renesas electroni cs data sheets or data books, etc. "standard": computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment ; home electronic appliances; machine tools; personal electronic equipment; and industrial robots. "high quality": transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; safety equipment; and medical equipment not specifically designed for life support. "specific": aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or syst ems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct thr eat to human life. 8. you should use the renesas electronics products described in this document within the range specified by renesas electronics , especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas el ectronics shall have no liability for malfunctions or damages arising out of the use of renesas electronics products beyond such specified ranges. 9. although renesas electronics endeavors to improve the quality and reliability of its products, semiconductor products have s pecific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. further, renesas electronics products are not subject to radiation resistance design . please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas electronics produc t, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measu res. because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 10. please contact a renesas electronics sales office for details as to environmental matters such as the environmental compati bility of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, in cluding without limitation, the eu rohs directive. renesas electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of renes as electronics. 12. please contact a renesas electronics sales office if you have any questions regarding the information contained in this doc ument or renesas electronics products, or if you have any other inquiries. (note 1) "renesas electronics" as used in this document means renesas electronics corporation and also includes its majority-o wned subsidiaries. (note 2) "renesas electronics product(s)" means any product developed or manufactured by or for renesas electronics. http://www.renesas.com refer to "http://www.renesas.com/" for the latest and detailed information. renesas electronics america inc. 2880 scott boulevard santa clara, ca 95050-2554, u.s.a. tel: +1-408-588-6000, fax: +1-408-588-6130 renesas electronics canada limited 1101 nicholson road, newmarket, ontario l3y 9c3, canada tel: +1-905-898-5441, fax: +1-905-898-3220 renesas electronics europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k tel: +44-1628-585-100, fax: +44-1628-585-900 renesas electronics europe gmbh arcadiastrasse 10, 40472 dsseldorf, germany tel: +49-211-65030, fax: +49-211-6503-1327 renesas electronics (china) co., ltd. 7th floor, quantum plaza, no.27 zhichunlu haidian district, beijing 100083, p.r.china tel: +86-10-8235-1155, fax: +86-10-8235-7679 renesas electronics (shanghai) co., ltd. unit 204, 205, azia center, no.1233 lujiazui ring rd., pudong district, shanghai 200120, china tel: +86-21-5877-1818, fax: +86-21-6887-7858 / -7898 renesas electronics hong kong limited unit 1601-1613, 16/f., tower 2, grand century place, 193 prince edward road west, mongkok, kowloon, hong kong tel: +852-2886-9318, fax: +852 2886-9022/9044 renesas electronics taiwan co., ltd. 7f, no. 363 fu shing north road taipei, taiwan tel: +886-2-8175-9600, fax: +886 2-8175-9670 renesas electronics singapore pte. ltd. 1 harbourfront avenue, #06-10, keppel bay tower, singapore 098632 tel: +65-6213-0200, fax: +65-6278-8001 renesas electronics malaysia sdn.bhd. unit 906, block b, menara amcorp, amcorp trade centre, no. 18, jln persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: +60-3-7955-9390, fax: +60-3-7955-9510 renesas electronics korea co., ltd. 11f., samik lavied' or bldg., 720-2 yeoksam-dong, kangnam-ku, seoul 135-080, korea tel: +82-2-558-3737, fax: +82-2-558-5141 sales offices ? 2011 renesas electronics corporation. all rights reserved. colophon 1.0 |
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